Asic Design Engineer
Il y a 6 mois
Within the BBIC team, you will be responsible for the specification, design and validation of various modules linked to Sequans’ next chipsets generation. You will work closely with our other teams (software, signal processing algorithms and integration).
REQUIRED EXPERIENCE
Engineering degree
Minimum of 3 years experience of ASIC and/or FPGA development.
Good experience of Verilog/VHDL
Knowledge of synthesis and static timing analysis tools would be a bonus
Experience of implementing digital signal processing modules would be a bonus
Fluent written and spoken English
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