Back End Engineer
Il y a 6 mois
Working with an ASIC design team, you will participate in the development of next generation SoCs for 5G and 4G wireless network. You will be responsible for the physical implementation of the chip, from synthesis netlist to GDSII, for power and area optimized chips in advanced nodes (12 nm, 22 nm). You will also be responsible for the physical verification of the chip.
REQUIRED EXPERIENCE
Engineering degree
At least 4 years of experience in place and route
Experience in DRC, LVS and IR drop analysis
Knowledge of Cadence tools would be a bonus
Experience of chips with power gating would be a bonus
Experience of 12nm/22nm process would be a bonus
Fluent written and spoken English
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