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Senior Silicon Physical Design Engineer

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Senior Silicon Physical Design Engineer Application at Axelera AI, a deep‑tech startup building the next‑generation AI platform. Axelera AI has raised $120m and employs 220+ people across 17 countries, with offices in Belgium, France, Switzerland, Italy, the UK, and headquartered in Eindhoven, Netherlands. We launched the Metis™ AI Platform and have a strong pipeline exceeding $100m. Position Overview As a Senior Silicon Physical Design Engineer you will develop cutting‑edge, multi‑core in‑memory compute SoCs. You will handle all aspects of ASIC Physical Design—from RTL to GDS—including synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‑off, and formal verification. You’ll collaborate closely with architecture, RTL, and verification teams. Key Responsibilities Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. Generate constraints and optimize timing. Execute clock tree synthesis (CTS) and custom clock‑building techniques. Integrate IPs such as memories, I/Os, embedded processors, DDR, networking fabrics, and analog ICs. Use EDA tools including Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre. Develop automation scripts in Python, Tcl, and Bash, and contribute to flow development. Debug and solve technical challenges related to physical design. Collaborate with architecture, RTL, and verification teams. Qualifications 10+ years of experience in Physical Design (RTL to GDS). Strong communication and teamwork skills. Expertise in all aspects of physical design. Hands‑on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre). Proficiency in clocking techniques and CTS. Experience integrating IP across domains. Strong scripting skills in Python and Tcl. Proven problem‑solving and debugging capabilities. Fluent in English (spoken and written). Highly Preferred Experience in floorplanning and top‑level integration. Knowledge of chip‑package‑board co‑simulation and packaging. Experience working with EDA vendors to resolve tool issues. Understanding of semiconductor device physics and multi‑domain design. Location Flexible working arrangement: Work from one of our offices in Leuven (Belgium), Amsterdam or Eindhoven (Netherlands), Florence or Milan (Italy), or Bristol (UK) if you’re already based nearby. Work fully remotely from any European country (incl. the UK). Relocate with us to Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). Priority will be given to candidates based in Belgium or Italy. What We Offer Competitive compensation, pension plan, extensive employee insurances, and the option to receive company shares. We foster an open culture that supports creativity, innovation, and collaborative ownership with responsibility. Equal Opportunity At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI. Seniority level: Mid‑Senior, Employment type: Full‑time, Job function: Engineering and Information Technology, Industry: Semiconductor Manufacturing. #J-18808-Ljbffr