UVM Verification Engineer
il y a 4 semaines
UVM Verification Engineer
Job Overview:We are seeking a skilled UVM Verification Engineer to join our client's Digital Verification team in France. As a key member of the team, you will be responsible for working extensively within their UVM environment to assist on their High Speed SOCs.
Key Responsibilities:- Develop and implement UVM verification environments for High Speed SOCs
- Collaborate with the team to design and implement automated frameworks for verification
- Utilize SystemVerilog and other relevant tools to create and test verification environments
- Work closely with the ASIC verification team to ensure seamless integration of verification environments
- Stay up-to-date with the latest developments in UVM and SystemVerilog to ensure the team's verification environments remain cutting-edge
- Extensive knowledge of UVM verification and SystemVerilog
- Experience in automated framework implementation and ASIC verification
- Knowledge of high-speed interfaces, specifically Ethernet or similar
- SoC Verification experience preferred but IP verification is also acceptable
Our client offers a competitive rate and a dynamic work environment. If you are a motivated and experienced UVM Verification Engineer looking for a new challenge, please contact us with your updated CV and availability.
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