Rtl Design Manager

**REF: RTLDM**:
Montbonnot (Grenoble area) / Permanent

**To support our growth, we are hiring an RTL Design Manager**:
REF: RTLDM

**ABOUT KALRAY**:
Kalray is a European **leader in hardware acceleration**, with full-stack acceleration expertise: from silicon to complete system.

Our **MPPA® (Massively Parallel Processor Array)** architecture is the foundation of Kalray’s processor (30+ patent families, 15+ years of development) and acceleration cards that combine processing power, flexibility, and energy efficiency.

Our mission is to deliver open **data-efficient hardware accelerators** to power next generation of data-intensive, AI-driven systems and infrastructures. We offer off-the-shelf processors, acceleration cards, and specialized processor development.

With over **130 employees** and presence in France and Romania, Kalray is backed by top-tier investors and publicly listed on **Euronext Growth.**You’ll be part of a pioneering team that is shaping the future of computing with cutting-edge **processor architecture, software-defined solutions,**and **next-generation acceleration platforms.**

We offer a **fast-paced, inclusive, and collaborative environment** where ambitious experienced professionals and young talents can thrive—while enjoying the positive and inspiring lanscape of the Alps or the Côte d’Azur.

**WHAT YOU 'LL BE DOING**:
As an **RTL Design Manager**, you will lead the Hardware Design team (**up to 20** **engineers**) and oversee the entire development lifecycle of our next-generation high-performance processors, implemented on advanced technology nodes.

You will take **ownership of technical direction and team coordination**, guiding developments from early microarchitecture definition through to power-aware RTL design and synthesis. Your role will involve close collaboration with system architecture, physical design, and verification teams to ensure successful delivery of complex IP blocks and subsystems.

**Responsibilities**:

- Drive RTL design activities, from specification to implementation and debugging, across a variety of advanced SoC components.
- Contribute to architectural decisions in coordination with the system architecture team.
- Ensure design quality and consistency with PPA (Performance, Power, Area) goals, optimizing for area and power efficiency.
- Monitor and integrate industry trends and best practices in digital design.
- Coordinate with verification and physical design teams throughout all project phases to ensure seamless integration.

**WHAT WE ARE LOOKING FOR**:
**Skills**:

- Proven expertise in RTL design using VHDL or Verilog
- Solid understanding of clock/reset strategies, synthesis flow, SDC constraint development, formal verification, and CDC handling
- Fluent in technical English, both written and spoken
- Strong communication and reporting abilities, with the capacity to interface effectively across technical teams
- Experience in managing and mentoring teams, including junior engineers, contractors, and external partners

**Profile**:

- Master’s degree or PhD in Electrical Engineering, Embedded Systems, or a related field
- At least 10 years of experience in digital RTL design for ASIC or FPGA-based commercial products
- Bonus: Familiarity with SoC interconnects, high-speed interface integration (PCIe, Ethernet, DDR), or processor IP design/integration
- Autonomous, curious, and rigorous in your technical approach
- Excellent collaboration skills and a strong sense of team leadership**CONTRACT INFORMATION**:

- Type of contract: Permanent contract
- Starting date: As soon as possible
- Location: Montbonnot (Grenoble Area)

**WHAT WE CAN OFFER YOU**:

- Competitive salary & performance-based RSU (free shares)
- Hybrid work model
- Additional paid leave (RTT)
- Meal vouchers (Edenred)
- Premium health coverage (Malakoff Humanis)
- Sustainable mobility incentives
- Generous paternity leave
- Monthly team activities (laser game, hiking, sailing, karaoke) and large-scale company events

**RECRUITMENT PROCESS**:

- First interview with the manager
- Second interview with the team
- Final interview with HRD or CEO

**Equal Opportunity Statement**: