Design Architect
il y a 2 jours
Arteris enables engineering and design teams at the world's most transformative brands to connect and integrate today's system-on-chips (SoCs) that fuel modern innovation.
If you've held a smartphone, driven an electronic car, or powered up a smart TV, you've come in contact with what we do at Arteris. Here, the future is quite literally in your hands-and when it isn't, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter
Your primary focus will be on developing cutting-edge cache coherent interconnect IP and ensuring seamless integration with other NoC interconnects, and system IP to support efficient and coherent communication between multiple processor and accelerator cores and functional units. You will collaborate closely with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions.
Cache Coherency Architecture:
• Develop comprehensive and scalable cache coherency architectures that align with the overall System-on-a-Chip (SoC) design
• Analyze our customer's requirements for cache coherent system architectures, also considering partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on industry wide standards like CXL, UCIe and PCIe
• Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture
• Help to optimize Cache Coherency Architecture and uArchitecture within the NoC to minimize latency and improve BW
# Collaborate with hardware and software teams to verify and optimize cache coherency mechanisms
# Support the emulation teams testing and debugging to validate cache coherency behaviors under various scenarios for functional correctness and performance
# Collaborate with hardware design, software development, and system architecture teams to understand their needs and issues
• Prepare detailed technical documentation, including architecture specifications and design guidelines/white papers.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
• Experience in cache coherency verification and validation techniques.
• Joining our team as a Cache Coherency Architect for our NoC IP development offers a unique opportunity to contribute to the creation of state-of-the-art semiconductor solutions. With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.
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