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Verification Engineer
Il y a 2 mois
Missions
Principales :
* Conception et mise en œuvre de plans de vérification pour valider les composants et systèmes embarqués.
* Développement de l'environnement de vérification en UVM.
* Écriture et exécution de tests en C embarqué sur des plateformes d'émulation.
* Analyse des résultats et debug de niveau système.
* Collaboration étroite avec les équipes de conception firmware et hardware pour assurer la cohérence et la qualité des systèmes développés.
Annexes :
* Participation à l'amélioration continue des process et outils de vérification.
* Veille technologique sur les méthodes de vérification et les outils associés.
À maîtriser :
* UVM (Universal Verification Methodology)
* Langages : C embarqué
* Outils de simulation et d'émulation : Questa, Veloce
Environnement technique global :
* Systèmes d'exploitation : Linux
* Versioning : Git
* Compilation : GCC, Makefile
* Autres : Bash, concepts de cache L1/L2, NOC (Network On Chip)
* Processeur : Cortex M7
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