DFT Engineer

il y a 1 mois

Paris, France EASY PARTNER Temps plein

Missions

Principales :

* Concevoir et implémenter des stratégies de Design For Testability (DFT) pour les microprocesseurs HPC en utilisant des outils avant-gardistes comme Siemens Tessent.

* Collaborer étroitement avec les équipes de développement pour intégrer efficacement les solutions DFT dans l'architecture des puces.

* Participer activement à la vérification, au debug et à l'optimisation des patterns DFT générés.

Annexes :

* Contribuer à l'évolution de l'environnement technique par la veille technologique et la suggestion d'innovations.

* Assurer un support technique aux équipes indiennes pour le déploiement des solutions DFT.

Stack technique

À maîtriser :

* DFT hiérarchique avec Siemens TestSense

* Outils Synopsys et Cadence pour la génération de patterns ATPG et la simulation

* Compréhension profonde du processus de ramp-up de silicium

Environnement technique global :

* Technologie de gravure avancée (7 nm, évoluant vers 3 nm)

* Outils de vérification fonctionnelle

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