Senior / Lead Digital IC Design Engineer (ASIC full flow)

il y a 6 jours


Paris, Île-de-France IC Resources Temps plein

Working for an innovative Semiconductor company in Grenoble, there is an exciting opportunity as a Senior Digital Design Engineer.

As a Senior Digital Design Engineer, you will play a key role in defining and executing the entire ASIC design process. Candidates should possess extensive experience in IP design & development across various stages including concept creation, architecture definition, RTL design, implementation, synthesis, STA (timing), DFT, and tape-out/release.

Moreover, the company offers a welcoming and cooperative work environment, fostering a sense of belonging.

Skills / requirements:

  • Degree / Masters / PHD in Electronics / Micro-electronics / Physics, or related fields.
  • Minimum of 10 years' experience in digital design.
  • Proficiency in RTL design (Verilog / VHDL, SystemVerilog) for ASIC / FPGA.
  • Demonstrated expertise in tape-out, IP development, and delivery processes.
  • Familiarity with the complete digital design flow, from RTL to GDS.
  • Experience in physical design, implementation, place & route (P&R) for back-end processes.
  • Knowledge of DFT - APTG / MBIST, etc.
  • Skills in STA, Timing Closure, and managing timing constraints.
  • Competence in synthesis and power-related aspects.
  • Strong understanding of verification processes using system verilog and UVM.
  • Background in embedded software development and firmware.


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