Verification Engineer
il y a 3 semaines
Verification Engineer
Location: Grenoble, France
Salary: Competitive Salary + Benefits
I am seeking a Verification Engineer that wants to join a rapidly growing company, working across multiple industries such as automotive, AI, satellite control systems and more
As a core member of the verification team, you will:
- Create UVM Verification IPs (VIPs) and write detailed verification plans.
- Verify complex SoCs and IPs, developing verification environments using SystemVerilog, UVM, and other methodologies.
- Mentor and guide junior engineers.
Required Expertise:
- Strong experience with SystemVerilog testbenches and UVM development.
- Solid understanding of SoC architectures and RTL design languages (VHDL, Verilog).
- Proven ability to perform functional verification for IPs and SoCs.
- Familiarity with Formal Verification and VAS tools.
Additional Skills:
- Knowledge of Python scripting.
- Experience with object-oriented programming.
- Background in ASIC or FPGA design.
Apply now and be a part of a company that values creativity, collaboration, and technical excellence To apply, please contact Meg Evans at IC Resources.
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