Senior Physical Implementation Engineer
Il y a 6 mois
Full time, based in Sophia Antipolis, France._
**J**ob description**
Within the Physical Implementation team, you will be in charge of doing the ASIC physical implementation of eFPGA IP architectures to bring them into production. You will also contribute to the development, improvement and maintenance of our internal design flow. You will participate in the development and implementation of new innovative eFPGA features in collaboration with the different entities of the R&D team.
This is a challenging position and an opportunity to work within a highly qualified team. You will get the chance to work on one of the most exciting new semiconductor products and on the most advanced process nodes (from 180nm to 5nm and beyond).
**Desired skills and experience**
- 10+ years of relevant experience in ASIC physical implementation (Front-End and Back-End)
- In depth knowledge of digital back-end EDA tool flows. Synthesis, Place and Route, STA, Formal-Verification and Signoff checks (LVS/DRC/EM-IR/ )
- Knowledge of Synopsys tool (ICC, ICC2, Primetime, StarRC, etc.) is a must. Knowledge of Mentor Graphics Calibre and Cadence tools are a plus.
- Knowledge of Power-management concepts is a must
- Knowledge of DFT concepts (scan, BIST, patterns generation,) is required
- Experience at IP level and IP integration at top level
- Experience with simulation tools is a plus
- FPGAs architecture and FPGAs software knowledge is a plus
- Experience on advanced technology nodes, such as 28nm, 16nm, 14nm and below is required
- Experience with C++, make files, scripting languages such as Tcl, Python and bash
- Technical background in RTL design (VHDL, Verilog, SystemVerilog) and RTL synthesis is required
- Good listening and communication skills
- Self-reliant and solid team player skills
- Good analytical and problem-solving skills
- Good written and spoken English is mandatory
- MSc or PhD in Electrical Engineering or equivalent
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