Optimising Ferroelectric

**Optimising ferroelectric (FE) memory properties by interface engineering**:

- Réf
- **ABG-112134**
- Sujet de Thèse- 15/03/2023- Contrat doctoral- Institut des Nanotechnologies de Lyon- Lieu de travail- Métropole de Lyon - Auvergne-Rhône-Alpes - France- Intitulé du sujet- Optimising ferroelectric (FE) memory properties by interface engineering- Champs scientifiques- Sciences de l’ingénieur
- Electronique
- Physique
- Mots clés- ferroelectricity, non volatile memory, nanoelectronics**Description du sujet**:
In the context of development of non-volatile memories ferroelectric (FE) material-based memories represent a challenging path considered to replace the existing Flash memories. They indeed present a very low consumption which is essential for on-board devices. However up-to-date a large implementation of such materials has been hindered by obstacles among which wake-up or fatigue (resp. opening and closing of the writing/reading window upon cycling) as well as imprint (shift of the hysteresis cycle P(V) upon cycling) which are related to the presence of defects. These defects, which affect device performances and life cycle are related to the electrode/FE material interfaces.

**Prise de fonction**:

- 02/10/2023**Nature du financement**:

- Contrat doctoral**Précisions sur le financement**:

- Bourse MESR (environ 2000 euros brut)**Présentation établissement et labo d'accueil**:

- Institut des Nanotechnologies de Lyon**Site web**:
**Intitulé du doctorat**:

- Thèse de Doctorat de l'Université de Lyon**Pays d'obtention du doctorat**:

- France**Etablissement délivrant le doctorat**:

- INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON**Ecole doctorale**:

- Électronique, électrotechnique, automatique (eea)- Master degree (or equivalent) in physics or material science or nanocale engineering preferentially with a thesis related to thin films
- Strong interest in experimental physics
- Experience in processing, developing and characterizing thin films
- Experience in thin film deposition techniques (PVD, CVD, ALD..) would be a plus
- Have a solid understating of physics and of semiconductor devices
- Fast learner, handson and flexible attitude
- High degree of responsibility while collaborating with team and lab mates and other lab staff
- Good management skills, good presentation skills, excellent written and oral English level (among nonnative English speakers, equivalent TOEFL score of 100 or higher)- 28/04/2023