Cpu Design Engineer
Il y a 2 mois
**Your role**:
Join our team as a CPU Design Engineer and collaborate with our IP team, working closely with Guillaume Bru from the French Design Center, Xubin Tan from the Barcelona Design Center, and CPU Architects based in the UK - Ben Fletcher, Tariq Kurd, etc.
Your primary focus will be on the recently launched Out-of-Order core project and memory subsystems. You will also have the opportunity to contribute to cutting-edge design projects, participate in the development of next-generation architectures, and work with our proprietary CodAL language.
**Requirements**:
**What we need**:
- Good knowledge of modern CPU architectures (ideally RISC-V) and micro-architectures, or alternatively track of records in the design of complex pipelined designs
- Hands-on experience with at least one Hardware Description Language (preferably - Verilog/SystemVerilog)
- Good knowledge of Out-of-Order core development and multicore cache coherence
- Understanding of the CHI protocol
- Sharp understanding of physical implications when designing at a higher level of abstraction (digital design synthesis and implementation flow)
- Skills to design and optimize a module around a given PPA point
- Practical expertise in versioning tools (preferably git)
- Proficiency in scripting languages (Shell, Python, Tcl)
- Practical usage of Linux
- Proficiency in digital design synthesis and implementation flow
**Benefits**
**Who is Codasip**:
We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.
Our processor cores are based on the RISC-V open architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.
**What’s in it for you?**:
We can offer you a chance to grow by providing variety in your day-to-day, autonomy to be creative with solutions in your role and really make a direct impact on the future custom compute revolution.
**Some useful links**:
Codasip’s approach to custom compute
Efficiently managing tagged memory for RISC-V
Understanding RISC_V virtual memory
CHERI demo at Embedded World 2024
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