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Digital Design Engineer
il y a 5 heures
1 day ago Be among the first 25 applicants Your primary mission will be to develop AICO’s new compute architecture in RTL. This is an innovative NPU (Neural Processing Unit) architecture dedicated to inference of Spiking Neural Networks (SNNs) for computer vision in embedded systems. The goal of this architecture is to be highly energy-efficient while maintaining competitive latency and preserving inference quality. You will also be involved in developing the architecture’s interfaces (MIPI, CSI, PCIe, etc.). You will also participate in RTL verification of the architecture’s functionality. You will also be responsible for building FPGA demonstrators (primarily on AMD Xilinx) that showcase this architecture, including interfaces with sensors, displaying results on a screen, etc. This task will therefore include porting the RTL architecture to the board using Xilinx tools (Vivado, Vitis, etc.), on-board debugging (ILA), and setting up the demonstration environment. You may also contribute to developing drivers to communicate with this compute architecture from a co-processor. You will also contribute to defining the chip specifications (target process technology, interface types, die size, speed, etc.) for the chip that will be produced based on this architecture. You must have at least 3 years of experience in digital design on ASIC and/or FPGA. You must have excellent knowledge of RTL programming. Good knowledge of VHDL is a plus. You must have already contributed to building an FPGA demonstrator (personal projects are accepted). You must be familiar with functional verification (testbenches, simulation) and with on-board FPGA debugging. You are comfortable with timing constraints and timing closure, and have a basic understanding of CDC (Clock Domain Crossing). You must be familiar with AXI-type interconnects (AXI4/AXI-Lite), DMA, and interrupts. Good knowledge of AMD Xilinx FPGA design suite is a plus. Good knowledge of Zynq and Versal architectures (AMD Xilinx) is a plus. Good knowledge of (low-level) C/C++ and Python is a plus. Good knowledge of Linux development (drivers, device tree, userspace interaction) is a plus. Good knowledge of machine learning, and more specifically neuromorphic computing (SNN, etc.), is also a plus. Prior exposure to the ASIC flow (synthesis/STA/PPA) is a plus. Recruitment Process A first “fit” interview, during which we will introduce AICO and the position you are applying for, and we will invite you to introduce yourself—your background, your projects, and your ambitions at AICO. We will also discuss your personality, the work environment you are looking for, etc. Finally, we will go over the practical aspects of the role (salary, mobility/relocation, remote work, etc.). A second technical interview, during which we will assess the skills relevant to the role. This will include questions about your technical knowledge as well as a technical test representative of the missions you would be assigned. A third interview, which will be an opportunity to meet other members of the team, review the first two interviews, and dive deeper into any points that require further discussion. After this third interview, we will get back to you with an answer as quickly as possible. Paris, Île-de-France, France Seniority level: Mid-Senior level Employment type: Full-time Job function: Other Industries: IT Services and IT Consulting #J-18808-Ljbffr
