RTL Design
il y a 8 heures
A leading technology company in Marseille is seeking an individual skilled in Verilog RTL design to integrate various IPs like PCIe with vendor PHY modules. Responsibilities include verifying the integration in dedicated environments, developing test cases, and supporting customers globally. The ideal candidate must be capable of proposing process improvements and maintaining traceability between specifications and verification outcomes. This role requires a detail-oriented person who can track productivity metrics and report on project progress.
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Design & Verification Engineer
il y a 8 heures
Marseille, France Rambus Temps pleinDesign & Verification EngineerCompany: RambusLocation: FranceJob Type: Full-timeSeniority Level: Mid‑Senior levelIndustry: Semiconductor ManufacturingOverviewRambus, a premier chip and silicon IP provider, seeks an exceptional mid‑level Design and Verification Engineer to join the PHY integration team in France. The successful candidate will participate...
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Design & Verification Engineer Rambus
il y a 8 heures
Marseille, France Semiconductor Engineering Temps pleinResponsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated simulation environment Development and support test cases of different verification environments Support worldwide customers on the IP integration Get familiar to existing verification process,...
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Design & Verification Engineer - PCIe/IP ASIC (Hybrid, Equity)
il y a 8 heures
Marseille, France Rambus Temps pleinA leading semiconductor company in France is seeking a mid-level Design & Verification Engineer to join their PHY integration team. The role involves RTL design and verification for PCIe Controller Soft IP development. Ideal candidates will have over 6 years of experience in ASIC/VLSI verification and proficiency in Verilog and SystemVerilog. Offering a...
