Senior Research Engineer: AI-Assisted Hardware Design and Simulation
il y a 2 semaines
Job Title: PhD Position in AI-Assisted Generation of High-Level Models and Simulators
Category: Electronics components and equipments
Contract: Fixed-term contract
Socio-professional category: Non Cadre
Contract duration (months): 36
Job description:
The design and validation of digital circuits rely heavily on simulation tools. These tools employ different levels of abstraction to facilitate hardware/software co-design and co-validation. Architecture simulators, known as Instruction Set Simulators (ISSs), provide high-level abstraction for fast functional verification and early design space exploration, whereas Register Transfer Level (RTL) simulators offer detailed circuit-level implementation for accurate analysis but with longer simulation times.
Hardware designers often face accelerated development schedules and tool/resource constraints, leading them to start with RTL development and defer ISS construction. However, as the design process advances, the need to create ISSs becomes apparent, particularly for tasks such as software validation and design space exploration of next-generation hardware. Creating ISSs manually presents significant challenges, including time-consuming and error-prone processes. Ensuring equivalence between ISS and RTL adds further complexity.
The generation process of an ISS primarily involves extracting architectural states and deriving instruction execution functions. An ISS is then constructed by seamlessly integrating the architectural states and the instruction execution functions, ensuring an accurate representation of the hardware's functional behavior.
The goal of the thesis is to design a methodology implemented in a tool that takes low-level RTL models as input and automatically generates an ISS by leveraging recent advances in machine learning, such as Graph Neural Networks, and compilation flows, like MLIR, in the field of electronic design automation (EDA). The expected result is a complete flow for the automatic generation of ISS from RTL, ensuring semantic consistency between the two levels.
The results of this thesis will be presented at international conferences and in scientific journals.
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