Senior IP Qualification Engineer
il y a 4 semaines
The Role
At Arm, we develop cutting-edge SoC (system on chip) that embeds the latest Arm Compute Sub-System IP and other various IPs from external companies.
We are seeking a skilled and dedicated senior engineer to join our IP Qualification team and help verify Third-Party IPs before they are embedded in SoC.
Such TPIP include standard-cells, I/O, SRAM/ROM memories, PLL, sensors, and sub-system interfaces like LPDDR, USB, Ethernet, or PCIe.
Responsibilities:
You will ensure that the RTL design and related EDA models of the TPIP align with EDA tools used in Arm SoC design flow.
You will verify that the methodology used for IP design and modeling aligns with Arm SoC flow requirements.
You will use, improve, or develop Tcl scripts and run them with EDA tools from major providers for SoC flow steps, including functional and low-power verifications, synthesis, automatic Place&Route, and Static Timing Analysis.
Required Skills and Experience:
- Five years of post-master degree work experience in RTL, lower-power, and gate-level functional verification with System Verilog, static low-power verification (UPF-1801) at IP/Block or SoC level.
- Experience in code RTL code Lint, Elaborate, and CDC/RDC verification.
- Scripting for tasks automation with Shells (Bash), TCL, Python, or any other language.
- Excellent interpersonal skills, strong initiative, and openness to engaging and learning various IP sophisticated SoC reference design flow.
Nice To Have Skills and Experience:
- Experience in DFT and STA with SDC constraints.
- Experience in Synopsys-VIP usage for Interface IP verification.
- Exposure to physical implementation.
In Return:
We offer a friendly and high-performance working environment, with a competitive benefits package in France, including private medical insurance, 25 days annual leave, 20-day sabbatical every four years, supplementary pension, and reduction in working hours.
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