Senior Verification Engineer
il y a 2 semaines
We are seeking an experienced UVM Verification Engineer to join our team at IC Resources. As a key member of our verification team, you will be responsible for developing and implementing verification environments, VIP components, and training other engineers.
Key Responsibilities:- Design and develop verification environments using SystemVerilog and UVM methodology
- Develop and implement VIP components
- Provide training and support to other engineers
- Collaborate with cross-functional teams to ensure successful project delivery
- 3-5+ years' experience in IP or SoC verification
- Confident knowledge of SystemVerilog and UVM methodology
- SoC architecture and bus communication protocols knowledge
- OOP and scripting skills
- Fluent English and preferably French
- Master's Degree a bonus
If you are a motivated and experienced UVM Verification Engineer looking for a new challenge, please contact Rob Hudson at IC Resources for a discussion.
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