Senior Engineer

il y a 7 heures


Antibes, Provence-Alpes-Côte d'Azur, France Arm Limited Temps plein
Job Title: Senior Engineer - RTL Design Verification

Arm Limited is seeking a highly skilled Senior Engineer to join our IP Qualification team. As a Senior Engineer, you will be responsible for verifying the RTL design and related EDA models of Third-Party IPs (TPIPs) before they are embedded in System on Chip (SoC) designs.

Responsibilities:
  • Ensure that the RTL design and related EDA models of TPIPs are in line with EDA tools used in Arm SoC design flow.
  • Verify that the methodology used for IP design and modeling aligns with the Arm SoC flow requirement.
  • Use, improve, or develop Tcl scripts and run them with EDA tools from major providers for SoC flow steps.
  • Analyze deviations and share them with SoC design teams for review and eventually report them to IP providers for update.
  • Participate in continuous improvement discussions.
Requirements:
  • Five years of post-master degree work experience in RTL, lower-power, and gate-level functional verification with System Verilog, static low-power verification (UPF-1801) at IP/Block or SoC level.
  • Experience in code RTL code Lint, Elaborate, and CDC/RDC verification.
  • Scripting for tasks automation with Shells (e.g. Bash), TCL, Python, or any other language.
  • Excellent interpersonal skills, strong initiative, and open to engaging and learning various IP sophisticated SoC reference design flow.
What We Offer:
  • A friendly and high-performance working environment.
  • A competitive benefits package in France, including private medical insurance, 25 days annual leave, 20-day sabbatical every four years, supplementary pension, and reduction in working hours.


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