Senior DFT Engineer

il y a 2 semaines


Grenoble, Auvergne-Rhône-Alpes, France RHESO Temps plein

Job Description:

We are seeking a highly motivated Senior DFT Engineer to join our team at RHESO.TECH. As a key member of our Design Team, you will be responsible for the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

Responsibilities:

  • Lead DFT architecture and implementation for complex SOC designs in advanced sub-20nm CMOS processes.
  • Develop and execute DFT flows, including HW DFT insertion, test vector generation, and validation.
  • Analyze digital DFT metrics and solutions considering DFT requirements: test time, yield, and default rate.
  • Advise digital design engineers on creating testable functional modules.
  • Integrate DFT seamlessly with RTL design and physical implementation teams without SOC performance impact.
  • Define optimum DFT solutions with the industrialization team and provide ATPG test vectors for production testing.

Requirements:

  • You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years of hands-on DFT implementation experience in complex digital and/or SOC circuits and solid knowledge in RTL design.
  • You command scripting languages like TCL, Perl, Python, and have experience with ATPG, BIST, ECC, and Redundancy.
  • You have hands-on experience with ASIC test methods and on-silicon physical and electrical defects.
  • You have a strong understanding of memory tests, logic tests (boundary scan, ATPG), JTAG (IEEE1149.1, IEEE1149.3), and Cadence DFT design flow.
  • You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, and communicate fluently in oral and written English.

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