Senior Analog IC Design Engineer

il y a 1 mois


Paris, Île-de-France SCALINX Temps plein
Job Title:

PLL Analog IC Design Engineer and Technical Leader

Job Summary:

SCALINX's design team is seeking a dynamic and experienced analog designer to contribute to the chip/block level architecture definition and implementation.

Key Responsibilities:
  • Focus on the architecture and design of high-performance RF PLL.
  • Lead and support analog design work-packages from transistor schematic to GDSII.
  • Drive, in close collaboration with the analog design and layout team, the specifications of the IC analog sub-blocks to achieve the best area/power/performance trade-off.
  • Contribute to the design and verification methodology at chip level and sub-blocks level.
  • Define the test strategy of the analog part(s) under his/her responsibilities and drive its implementation.
  • Work in a team to successfully design a state-of-the-art IC.
Requirements:
  • MSc or PhD in Electrical Engineering or equivalent.
  • 10+ years of hands-on experience in chip-level and circuit-level architecture definition, transistor level design, and verification.
  • Solid background in low jitter LC based PLL design on integrated circuit for high-speed and high-performance ADC/DAC data converters.
  • Strong experience in PLL design in advanced node CMOS/FDSOI silicon technologies (22nm and beyond).
  • Very good vision of the entire analog/mixed-signal IC design flow from transistor schematic to GDSII.
  • Experience in the design of high-speed, low noise and interference robust analog and mixed-signal circuits.
  • Solid knowledge of analog design and simulation tools (Cadence Spectre).
  • Strong experience with Cadence design flow.
  • Fluent communication in English (oral and written).


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