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[CONTRACT] ASIC Verification Engineer
il y a 3 semaines
Job Description Job Title: UVM Verification Engineer Duration: 6 months initial Location: France Remote: Up to % available Start: ASAP Job Description Our client is a pioneer in design and development of space-grade SoC and FPGA Devices in France. As a rapidly growing company, they are looking to continue building its software and hardware teams. They are looking for ASIC Verification Engineers where they will join the client's hardware team based in the Paris region. The mission is to develop different IPs on ASICs and FPGAs. Teamwork skills will be decisive in the selection of the candidate. REQUIRED SKILLS -Extensive background in SoC Verification -Knowledge of RTL languages: Verilog or VHDL. -Strong background in UVM Verification -Good communication skills in English and French. -Adherence to deadlines. -Having a tape-out experience is a plus.
