Cad Io Esd Design Engineer
il y a 2 jours
Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization? We offer all that and more at Microchip Technology, Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our
Vision, Mission, and 11 Guiding Values
; we affectionately refer to it as the
_Aggregate System_ and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over
30 years of quarterly profitability
without a great team dedicated to empowering innovation. People like you.
Visit our
careers
page to see what exciting opportunities and company
perks
await
**Job Description**:
The team is also responsible for the design and validation of the ESD protections for the CAD IOs team and for the different BUs.
As a member of Microchip’s I/O Design Team, your responsibility will be to perform ESD reviews, and support BUs designers (cell and chip level) on ESD protection design. You will participate in all aspects of the reviews, like simulations and usage of different appropriate CAD tools.
The IO ESD engineer duties include:
- ESD review cells & products using relevant CAD tools (PERC, Redhawk)- Support / interface with Analog and Physical designers- Electrical simulations on specific structures- Scripting / coding for automation- Analysis ESD TLP report to define ESD protection strategy- Edit ESD review report- Interface with and support architect designers, PE, technology development and foundries teams.- Participate to the development of ESD test structures and define silicon characterization plans.
Requirements/Qualifications:
Preferred Skills- Experience in ESD protections design- Understanding of ESD and latch-up requirement for layout- Experience in PERC Tool- Experience in extractors (StarRC, Calibre PEX)- Experience Cadence Virtuoso- Experience in electrical simulation- Experience in Python coding and scripting is a plus- Good oral and written communication skills- Ability to communicate using English is mandatory
Education- B.S minimum requirement, Electrical Engineering; M.S. PhD a plus
Experience- Minimum 5-10 years of experience in ESD, IO cells design, or PDK, Physical Verification
Travel Time:
0% - 25%
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