Analog Power Management Design Manager

il y a 2 jours

Sophia Antipolis, France NXP Semiconductors Temps plein

The goal of the SCE (Secure Connected Edge) team within NXP is to become the leader in its market by leveraging its unique portfolio of IP from NFC and Secure Elements, NFC and UHF tags, WiFI, UWB and Bluetooth products to deliver solutions that are better than the sum of its parts.

Working in a fast paces mobile environment, we are looking for an outstanding manager to lead our global Analog Power Management team.

The person must have excellent communication skills and proven ability to collaborate across organizational and geographical boundaries, and the ability to make timely decision in face of incomplete information, managing risks and setting priorities driven by business impact

The role will also involve frequent communication with key customers for detailed reviews

**Responsibilities**
- Lead a global team of analog designers that design power management solutions for System on Chip design to meet exacting area and power goals.
- Responsible for power management design of NFC UWB and BT/BLE products
- With the product managers, system and IC architects define the roadmap that ensures the products continue to lead the competition
- Develop the expertise of the team and drive innovation
- Define key specifications, drive feasibility and design and estimates on area, performance and timeline
- Drive the team to meet aggressive schedules without sacrificing quality
- Work with other teams on the project (Digital, Firmware, Layout, Test ) to ensure the success of the overall product
- Work with validation and systems team to ensure that the silicon is meeting the key performance targets

**Profile**
- Masters Degree in Electronic/Electrical Engineering
- Minimum of 10 years experience in the design of analog blocks and systems for power management
- Experience with leading a global team of analog engineers
- Proven track record in delivering working silicon for high volume products
- Solid fundamentals of transistor level integrated circuits and device physics.
- Knowledge of layout matching and parasitics, latch-up, ESD, etc.
- Rigorous and methodical with good analytical skills for debugging issues in design and on silicon
- Familiarity with EDA design tools and Cadence design environment

More information about NXP in France...

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