Principal Engineer

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**Job Description**:
To support Physical Design-related project activities for multiple key business units, including MPU32, MCU32, and WSG. The product's focus is on 32-bit microprocessors, microcontrollers, and wireless design and implementation.- Implement all aspects of physical design from netlist to GDSII: floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification- Utilize hierarchical systems-level design techniques to build designs exceeding multi-million gates.- Work with and improving on the place and route methodologies and low power methodologies.- Must be a self-motivated team player who can collaborate with multiple teams across a geographically diverse company to achieve desired design goals.- Timing closure support to maximize process node capability.- Clock tree setup/debug and synthesis for optimal QoR.- General physical implementation procedures.- Multi-voltage island-based floorplan design and support.- Flow development and automation implementation.- Delivering Physical Verification-clean designs.- Die size estimation and Bondout approval.- Interfacing with external vendors and IP sources to resolve problems.- Work with members from international design/implementation teams.

Requirements/Qualifications:
- Masters/Bachelor’s Degree in Electrical / Electronics Engineering.- Minimum of 7 years or more applicable technical experience in the physical and timing-related aspects of IC design.- Detailed knowledge of one or more of the following tools: ICC, ICC2, Innovus, Fusion Compiler, or Redhawk- Proficiency in Tcl scripting- Excellent debugging and analytical skills- Good verbal and written communication skills and strong interpersonal skills

The design task requires experience in the following Physical Design-related activities:
- Advanced knowledge of VLSI logic principles, clock tree synthesis & debug, and design timing closure.- Advanced knowledge of place and route methodologies and low power methodologies.- Experience with 40nm or 28nm technologies is required.- Recent experience with leading full-chip Physical Design activities.- Detailed systems-level floorplanning.- Power network planning.- Multi-voltage/low power implementation techniques.- Power integrity and reliability (EM & IR) analysis.

Travel Time:
0% - 25%