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Senior Low Power Dft Engineer
il y a 2 semaines
**Context**:
GreenWaves is a fabless semiconductor company founded in 2014 and based in Grenoble, France. We design and market ultra low power processors for energy constrained products such as hearables, wearables, IoT & medical monitoring products.
GreenWaves’ system-on-chips enable companies to develop and bring to market products with new to world features enabled by state of the art machine learning and digital signal processing techniques. Our leading edge development tools enable audio and machine learning developers to productively harness the power of GAP processors.
GreenWaves GAP9 processor powers features such as neural network based noise removal and adaptive noise cancellation, multi-channel spatial sound and listening enhancement technologies in next generation earbuds and headphones with market leading energy efficiency.
As a growing, talented and highly multicultural team with sharp personalities, we are proud of what we do and how we do it. Our non-hierarchical culture means living our core values: ownership, collaboration, agility, dedication to customers and engagement. We believe that work is more than just a to-do list. You are empowered to build a leading company and to share its success
We are looking for talented, enthusiastic, and committed people to be a part of our GreenWaves family.
**Responsibilities**:
We are looking for an experienced R&D engineer to architect, design and verify the design-for-testing infrastructure of our next generations of chips. In close relationship with SoC architects and the whole IC design team, you will:
- Specify DFT architecture and insertion: scan (stuck-at, at-speed, scan compression), memory BIST
- Implement and verify the DFT in the chips
- Define the chip power intent (UPF) for physical implementation
- Optimize DFT to minimize impact on functional mode (timings, power)
- Support physical implementation engineers for aspects related to DFT and to low-power checks
- Generate and verify (simulation) test patterns
- Optimize test coverage and test time
- Support test engineers on test program setup and debug on industrial tester
This position requires numerous collaborations with the different departments of the Group (internal and external to the site): IC design, Boards, Embedded software, Application
**Required skills**:
- DFT techniques and associated EDA tools (e.g. Modus)
- Proficiency in UPF format
- LP checks and associated tools (e.g. Conformal LP)
- Efficient use of simulation tools (RTL, netlist, back-annotated netlist)
- Ability to work autonomously and proactively on assigned tasks
- Strong team spirit and communication, happy to collaborate and share with his teammates, even remotely. Eager to share skills and advice, eager to learn new skills
- Good level in English
**Desired skills**:
- Good knowledge of digital design flow, from RTL to GDS II
- UPF-aware RTL simulation
**Job Type**:Full time (CDI)**Job Category**:Engineering**Job Location**:Grenoble. France (Alsace-Lorraine near train/tram)**Remuneration**:Competetive compensation and stock option plan
