Senior Dft Engineer

Romain's team is currently looking for a **Senior DFT Engineer** that will hold a horizontal position within the Digital Design organization**.**

The purpose of the position is to technically handle DFT activities in Dolphin Design in ASIC Business Unit from architectre/specification to chip bring-up.

As the main point of contact in the company, the position includes technical support for customer pre/post-sales activities and deployment of state-of-the-art DFT design flow & methodologies. Interfacing with all necessary internal and external stake-holders, achieving his various missions will secure Dolphin Design product offering. She/he will be recognized as leading the digital design methodologies. He will also foster and drive the company to make our IPs and IP platforms easy to integrate within our customers design flows.

The job is located within the Digital Design Team in charge of ASICs development from architecture definition to front-end implementation.

**YOUR TASKS**:
**1. Project Execution**
- Specify, implement and drive DFT activities for ASIC and IP projects in order to guarantee technical consistency between products and design methodologies in order to be committed on the project milestones.
- Work closely with SoC architect to define the DFT strategy in order to ensure minimum test time in line with customer needs.
- Work with RTL, digital/analog, verification and physical implementation teams during DFT implementation.
- Work with cross functional groups to verify DFT implementation pre tape-out.
- Drive successful bring-up of test features post tape-out.

**2. Methodology**
- Lead the development and maintenance of the DFT design flows for ASIC/IP projects from architecture definition to physical implementation in order to target minimum test time for all Dolphin products.
- Add to the in-house expertise on DFT to consult with, educate, and train design staff members on DFT requirements on how to prepare new designs to work properly with Mentor Tessent DFT solutions.

**3. Customer**

Provide customer support and guidance for all DFT activities.

**4. Project**

Provide internal support and guidance for DFT activities. Participate in project set-up and execution working closely with project managers and others team members.

**THIS POSITION IS FOR YOU**:
You have a master degree in Electrical Engineering, Computer Engineering, Computer Science or related equivalent, with at least 8 years of experience in DFT.

**Required skills**:
**Knowledge**
- DFT SoC and IP architecture, design and implementation flows for minimum test time
- Memory BIST, Scan, Boundary scan, logic BIST, IJTAG protocol
- DFT infrastructure
- UPF standards: UPF1.0, 2.0, 2.1 and 3.0
- RTL coding
- Design and verification methodologies
- Gate Level Simulations
- EDA tools from Cadence, Mentor and Synopsys covering all steps of the flow
- Scripting : Tcl, Shell, Perl, Python
- Linux/Windows working environment

**Know-how**
- Require experience as a DFT architect, establishing state-of-the-art DFT strategy, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
- Require experience with development DFT infrastructure and usage of tool such as Tessent, Design Compiler, Tetramax.
- Require experience with silicon debug at the tester and board level.
- Experience in UPF design is a big plus.
- Experience in RTL coding including design checks (CDC, coding rules..) is a plus
- Experience with gate level simulation, low power design.

Salary package: Metallurgy agreement, executive status, 8 compensation time off, Time Savings Account, profit-sharing, payment for 60% of public transport costs, 0.25ct/km bicycle mileage allowance, luncheon vouchers
- Partial remote working possible._