Post-doctoral Research Visit F/m Enhancing Cache

Le descriptif de l’offre ci-dessous est en Anglais_ **Type de contrat **:CDD **Contrat renouvelable **:Oui **Niveau de diplôme exigé **:Thèse ou équivalent **Fonction **:Post-Doctorant **A propos du centre ou de la direction fonctionnelle**: The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc. **Contexte et atouts du poste**: This postdoc position will be funded by the Rakes and AllOpticall2 ANR Projects. These projects involve Inria Taran (Rennes/Lannion), INL (Lyon), Lab-STICC (Lorient), TIMA (Grenoble), CEA (Paris-Saclay), and C2N (Paris-Saclay). The Taran team has already a strong background in on-chip interconnects, and on the emerging interconnect paradigms (WiNoC, ONoC) targeted in this project. **Mission confiée**: **Subject** Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC. These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware-controlled memories containing copies of parts of the main memory (a.k.a caches) are used [1]. To keep these distributed copies up-to-date and synchronize the accesses to shared data, it requires to share information between some may if not all the nodes. This leads to increase the number of data transfers that must be supported by the interconnection media. Furthermore, these specific data transfers concern generally one source and several destinations, which correspond to multicast/broadcast communications. In parallel, technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to the Wireless Network-on-Chip (WiNoC) [2-3] and Optical Network-on-Chip (ONoC) [4-5] paradigms. These emerging technologies are showing significant advantages for broadcasting data (WiNoC) and low-latency communications (ONoC), whereas conventional Electrical Network-on-Chip (ENoC) is reaching a limit [6]. In this context, the main objective of this project is to explore how these emerging technologies can improve the efficiency of on-chip interconnection systems of shared-memory manycore architectures based on cache coherence protocols. We will study new cache protocols which are well adapted for the specific properties of hybrid interconnects. Model of communications for each media/technology will be defined, in terms of data transfer latency, power consumption, etc., and these models will be used at the operating system level to select the best media for each type of transfer. **Bibliography**: - M. MK Martin, M. D. Hill, and D. J. Sorin. "Why on-chip cache coherence is here to stay." Communications of the ACM 55.7 (2012): 78-89. - A. Karkar et al. “A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many - Cores”. In: IEEE Circuits and Systems Magazine 16., pp. 58-72, 2016. - M. F. Chang, et al., “CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect,” Proc. of IEEE Int. symposium on High - Performance Computer Architecture (HPCA), pp. 191-202, 2008. - A. Shacham, K. Bergman, and L. P. Carloni. "Photonic networks-on-chip for future generations of chip multiprocessors." IEEE Transactions on Computers, vol. 57.9 pp: 1246-1260, 2008. - J. Ortiz Sosa, O. Sentieys, C. Roland. A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. _Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)_, Oct 2018, Torino, Italy. pp.1-8 - J. Luo, C. Killian, D. Chillet, S. Le Beux, I. OConnor, O. Sentieys. “Offline optimization of wavelength allocation and laser power in nanophotonic interconnects”. In: _ACM Journal on Emerging Technologies in Computing Systems (JETC) _(2018). **Principales activités**: The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest. The goal is to improve performance and energy efficiency of on-chip interconnect in the context of manycore architectures, and we seek to find systematic methods to answer the ke