Senior Digital Design and Verification Engineer

il y a 1 mois

Rennes, France Silicon Labs Temps plein

We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

Overview:

As a Design & Verification Engineer focusing on digital design and verification of wireless PHY and MAC layer IPs and systems for low-power System-on-Chip IoT products, you will join a specialized team of IP/SoC engineers driving multiple wireless communications technologies such as Bluetooth Low-Energy, 802.15.4 Zigbee/Thread, 802.11 Wi-Fi and proprietary short-range wireless.

You will be part of a highly skilled and tight-knit team where everyone can have significant impact on, and responsibility for, the end product. The Rennes site is cross functional and therefore you’ll be interacting firsthand with software designers and customer support team. We strive to strike a good work/life balance and make our environment welcoming and fun, so we seek someone whose technical skills are matched by their interpersonal skills.

What You'll Do:

You will take designs through the complete development lifecycle from concept/study to silicon bring-up

Perform architectural studies to determine optimal hardware implementations of PHY and MAC layer designs to meet product requirements

Develop and review detailed and concise architecture and design specification documents

RTL logic design of modules using Verilog HDL. Designs may include protocol/MAC accelerators, FIR/CIC filters, signal acquisition, timing recovery, mixers, equalizers, FFTs, demodulators, FEC encoders/decoders, AGC…

Develop testbenches to verify the functionalities of IPs and system, both at block, sub-system and chip levels

Develop low level C-code Firmware for embedded processors

Prepare and hold architecture, design and verification reviews with technical staff throughout project lifecycle

Pre-silicon verification utilizing a combination of block/chip-level test benches and FPGA emulation

Validation/bring-up of designs on silicon, providing support to cross-functional teams

Mentor other engineers in either a technical or project lead role

What skills you need:

Master level degree in Electrical Engineering (Signal Processing background is a plus)

8+ years of professional experience in digital design and verification

Experience in implementing and analyzing fixed-point DSP and numerical processing elements

Verilog RTL design with emphasis on DSP/math-centric designs

Experience in block and chip-level verification and emulation

Good knowledge of UVM based verification methodology

Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools

Experience using Matlab or other high-level modeling language/tool for designing and evaluating communication systems and algorithms

Knowledge of scripting/language (perl, shell, tcl, python)

Excellent written and verbal communications skills (Fluent English)

What we offer:

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