SMTS Logic Design

il y a 1 semaine

AixenProvence, Provence-Alpes-Côte d'Azur, France Rambus Temps plein

Responsibilities

  • Develop IP features
  • Define reference design / example architectures to best demonstrate features of Rambus PCIe / CXL controller IP
  • Develop (Verilog) these designs
  • Perform simulation with various simulators
  • Perform FPGA synthesis implementation flow
  • Perform HW Test and debug on cutting edge platforms
  • Scripting for continuous integration and automation

Qualifications

Required:

  • RTL coding : Verilog / VHDL
  • Master’s degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
  • 2+ years of experience with RTL Design
  • Good English skills, communication skills, and willingness to work with an international team.

Additional Desirable Skills

  • RTL Simulation : Questa / VCS / NCSIM
  • FPGA flows : Vivado / Quartus
  • CI: Python / Jenkins / GIT

About Rambus

Rambus is a global corporation specializing in cutting-edge memory interface chips and Silicon IPs to enhance data center connectivity and resolve the bottleneck between memory and processing. With a rich history of semiconductor expertise spanning more than three decades, we stand out as a premier provider of high-performance solutions and breakthroughs that optimize the bandwidth, capacity, and security for AI and other data-demanding tasks. Our exceptional team serves as the cornerstone of our organization, propelling us forward to create forefront products and technologies vital for the systems of tomorrow.

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