SMTS Logic Design

il y a 4 semaines

AixenProvence, France Rambus Temps plein

Responsibilities

Develop IP features  Define reference design / example architectures to best demonstrate features of Rambus PCIe / CXL controller IP Develop (Verilog) these designs Perform simulation with various simulators Perform FPGA synthesis implementation flow Perform HW Test and debug on cutting edge platforms Scripting for continuous integration and automation

Qualifications

Required: 

RTL coding : Verilog / VHDL Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. 2+ years of experience with RTL Design Good English skills, communication skills, and willingness to work with an international team.

Additional Desirable Skills  
 

RTL Simulation : Questa / VCS / NCSIM FPGA flows : Vivado / Quartus CI : Python / Jenkins / GIT
 
 

About Rambus  
 
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. 
 

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