Internship Performance Debugging

Il y a 3 mois

Grenoble, France Inria Temps plein

Le descriptif de l’offre ci-dessous est en Anglais_

**Type de contrat **:Convention de stage

**Contrat renouvelable **:Oui

**Niveau de diplôme exigé **:Bac + 3 ou équivalent

**Fonction **:Stagiaire de la recherche

**A propos du centre ou de la direction fonctionnelle**:
The Inria Grenoble - Rhône-Alpes research center groups together almost 600 people in 22 research teams and 7 research support departments.

Staff is present on three campuses in Grenoble, in close collaboration with other research and higher education institutions (Université Grenoble Alpes, CNRS, CEA, INRAE,), but also with key economic players in the area.

Inria Grenoble - Rhône-Alpes is active in the fields of high-performance computing, verification and embedded systems, modeling of the environment at multiple levels, and data science and artificial intelligence. The center is a top-level scientific institute with an extensive network of international collaborations in Europe and the rest of the world.

**Contexte et atouts du poste**:
Performance debugging aims at identifying code regions that are both hot (take important part of execution time, hardware resources), and fat (performance can potentially be improved). Once such a region have been identified, understanding what causes the performance bug is crucial for fixing it. In particular, ability to point out instructions or dependences that are source of performance bottleneck is important. This requires the development of binary level tools and performance models that can map executed instructions to used hardware resources.

For this purpose, our team (CORSE) have developped several tools including:

- GUS: Dynamic code analysis using fast abstract simulator based sensitivity analysis

**Mission confiée**:
**Long term objective** is to improve the quality of feedback provided by GUS which should:

- automatically detect the source of bottleneck without requiring multiple runs
- highlight instructions involved in a performance bottlneck
- highlight the source of bottleneck (including dependencies when latency bound)
- provide high-level semantic of asm instruction behavior (induction variables, address computation, memory access, floating point arithmetic...)

**The intern will first** get to know GUS' code through a few simple developments such as:

- add a configuration file for describing basic features of the targeted/simulated architecture
- replace the shadow memory by an "ephemeral" hash-map that supports arbitrary sized labels
- enrich text-based feedback with color edges between instructions so as to allow highlighting data-flow or control flow information

**He will then work** on the long term objectives which constitute the core of the internship project.

**Principales activités**:
**Main activities include**:

- Read and experiment with related work
- Code development (C++, python)
- Write scientific papers

**Compétences**:
**Technical skills**:

- binary instrumentation
- instruction set architecture
- C++, Python

**Languages **:English & French (efforts for learning French is highly appreciated)

**Avantages**:

- Subsidized meals
- Partial reimbursement of public transport costs
- Leave
- Possibility of partly teleworking and flexible organization of working hours depending on the team needs and the internship agreement
- Professional equipment available (videoconferencing, loan of computer equipment, etc.)
- Social, cultural and sports events and activities
- Access to vocational training

**Rémunération**:
Gratification = 4,35€ gross / hour

**Informations générales**:

- **Thème/Domaine**: Architecture, langages et compilation
Système & réseaux (BAP E)
- **Ville**: grenoble
- **Centre Inria**: Centre Inria de l'Université Grenoble Alpes
- **Date de prise de fonction souhaitée**: 2024-11-01
- **Durée de contrat**: 5 mois
- **Date limite pour postuler**: 2024-10-01

**Consignes pour postuler**:
**Sécurité défense**:
Ce poste est susceptible d’être affecté dans une zone à régime restrictif (ZRR), telle que définie dans le décret n°2011-1425 relatif à la protection du potentiel scientifique et technique de la nation (PPST). L’autorisation d’accès à une zone est délivrée par le chef d’établissement, après avis ministériel favorable, tel que défini dans l’arrêté du 03 juillet 2012, relatif à la PPST. Un avis ministériel défavorable pour un poste affecté dans une ZRR aurait pour conséquence l’annulation du recrutement.

**Politique de recrutement**:
Dans le cadre de sa politique diversité, tous les postes Inria sont accessibles aux personnes en situation de handicap.

**Contacts**:

- **Équipe Inria**: CORSE
- **Recruteur**:
**A propos d'Inria**:
Inria est l’institut national de recherche dédié aux sciences et technologies du numérique. Il emploie 2600 personnes. Ses 215 équipes-projets agiles, en général communes avec des partenaires académiques, impliquent plus de 3900 scientifiques pour

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