Hardware Program Lead

You will join AICO as a Hardware Lead, responsible for leading the design and industrialization of our ASIC based on an innovative compute architecture (NPU-like) dedicated to Spiking Neural Network (SNN) inference for embedded systems. You will lead the Digital Design team (RTL/FPGA/ASIC engineers) and own the roadmap, specification, quality, and delivery of the chip. You will work closely with external partners (physical design/back‑end, foundries, packaging, test, IP vendors, etc.) to drive the project end‑to‑end through tape‑out and early bring‑up. In a small team, this is also a hands‑on role: you will contribute to architectural decisions, RTL and verification strategy, and key PPA (Power/Performance/Area) trade‑offs, while setting up robust development processes and ensuring execution. Key Responsibilities ASIC program leadership: define specs, plan and milestones (tape‑out, bring‑up), manage risks, track quality/cost/schedule. Technical leadership: review/validate architecture and micro‑architecture, drive PPA trade‑offs, define performance/power/area and interface requirements. Team leadership: manage and mentor RTL/FPGA engineers, run design reviews, prioritize work, raise engineering standards. Partner management: coordinate with physical design (synthesis/P&R/STA), DFT, verification, foundry, packaging, test, validation partners. Methodology & flow: establish/maintain ASIC development flow (lint, CDC, simulation, regressions, sign‑off criteria), configuration management and release process. Prototyping & validation: leverage FPGA prototyping/demos to de‑risk the ASIC and prepare bring‑up. Hands‑on RTL contribution: occasionally contribute directly to RTL development (implementing critical blocks, prototyping, code reviews/merges) and supporting the team on complex or time‑critical topics. FPGA demonstrator contribution: occasionally contribute directly to the building of FPGA demonstrators. Must‑Have 10+ years of experience in digital design with a strong emphasis on ASIC (FPGA experience is a valuable plus). Proven track record leading an ASIC program, including at least one supervised/led tape‑out (ideally through early bring‑up). Strong RTL expertise (VHDL and/or Verilog/SystemVerilog) and solid design practices (clock/reset strategy, synchronization, constraints, robustness). Strong understanding of the ASIC flow from architecture to sign‑off (even if back‑end is outsourced). Ability to drive PPA (Power/Performance/Area) trade‑offs and make pragmatic design decisions. Experience as a technical lead/manager: planning, prioritization, design reviews, cross‑functional communication. Experience working with external partners and producing/maintaining technical specs and deliverables. Nice‑to‑Have DFT exposure (scan, JTAG, BIST, coverage) or experience coordinating DFT partners. Structured verification experience (UVM, coverage, formal, CDC/lint tools). FPGA prototyping and board bring‑up/debug (ideally AMD Xilinx). SoC integration knowledge (AXI, DMA, interrupts, memory interfaces, interconnect). Embedded/Linux bring‑up (drivers, device tree) and lab validation experience. ML/SNN/neuromorphic background (bonus). Recruitment Process Our recruitment process consists of three interviews: A first “fit” interview, during which we will introduce AICO and the position you are applying for, and we will invite you to introduce yourself—your background, your projects, and your ambitions at AICO. We will also discuss your personality, the work environment you are looking for, etc. Finally, we will go over the practical aspects of the role (salary, mobility/relocation, remote work, etc.). A second technical interview, during which we will assess the skills relevant to the role. This will include questions about your technical knowledge as well as a technical test representative of the missions you would be assigned. A third interview, which will be an opportunity to meet other members of the team, review the first two interviews, and dive deeper into any points that require further discussion. After this third interview, we will get back to you with an answer as quickly as possible. #J-18808-Ljbffr