NPU RTL Design Engineer for FPGA/ASIC

il y a 13 heures


Paris, France AICO Technology Temps plein

A technology company in Paris is seeking a Mid-Senior Level Engineer to develop an innovative compute architecture in RTL for a Neural Processing Unit dedicated to machine learning. The role involves building FPGA demonstrators, establishing interfaces, and defining chip specifications. The ideal candidate has strong digital design and RTL programming skills, with experience in FPGA demonstrators and functional verification. A solid understanding of Xilinx tools and machine learning principles is also beneficial. Join a dynamic team making strides in neuromorphic computing.
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