Senior Verification Engineer, RISC-V CPUs
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Codasip is looking for experienced Verification Engineers for their design center in Villeneuve-Loubet, France. The role involves verifying RISC-V processors, developing test benches, and collaborating with engineering teams to deliver verification results.
Candidates should have a strong background in processor verification methodologies and programming skills in languages such as SystemVerilog, Python, and C++. This is an exciting opportunity to impact cutting-edge technology in a collaborative environment.
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