Senior Formal Verification Engineer
il y a 4 semaines
We are seeking a highly skilled Principal Engineer / Expert in Formal Verification to join our research team in Grenoble or Paris, France.
Role OverviewAs a Principal Engineer / Expert in Formal Verification, you will be responsible for developing and applying formal verification techniques for chip design and EDA tools, as well as system design. You will collaborate with interdisciplinary teams to integrate formal methods into design processes, research and implement innovative formal verification solutions for enhanced efficiency and scalability, and provide technical leadership and mentoring to junior engineers.
Responsibilities- Develop and apply formal verification techniques for chip design and EDA tools, as well as system design.
- Collaborate with interdisciplinary teams to integrate formal methods into design processes.
- Research and implement innovative formal verification solutions for enhanced efficiency and scalability.
- Provide technical leadership, mentoring junior engineers, and driving strategic tool development.
- Take a leadership position in establishing and growing the local team in Paris.
- Extensive experience in formal verification, especially in chip design and EDA tools.
- Strong industrial background and proficiency in hardware description languages (HDLs).
- Advanced knowledge of formal methods like model checking and symbolic execution.
- PhD in computer science, formal methods, or a related field.
- Excellent leadership and problem-solving skills, with a collaborative approach.
This is an exciting opportunity to join a leading research team dedicated to advancing formal verification methods in chip design and system-level verification. If you are a skilled engineer with a passion for formal verification, we encourage you to apply for this role.
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