Principal Engineer for Verification and Validation
il y a 3 semaines
We are seeking a highly skilled Principal Engineer for Verification and Validation to join our research team in Grenoble or Paris, France. The ideal candidate will possess deep expertise in formal methods applied to chip design and verification, including EDA tools, and system design.
Key Responsibilities:
- Develop and apply formal verification techniques for chip design and EDA tools, as well as system design.
- Collaborate with interdisciplinary teams to integrate formal methods into design processes.
- Research and implement innovative formal verification solutions for enhanced efficiency and scalability.
- Provide technical leadership, mentoring junior engineers, and driving strategic tool development.
Requirements:
- Extensive experience in formal verification, especially in chip design and EDA tools.
- Strong industrial background and proficiency in hardware description languages (HDLs).
- Advanced knowledge of formal methods like model checking and symbolic execution.
- PhD in computer science, formal methods, or a related field.
- Excellent leadership and problem-solving skills, with a collaborative approach.
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