Senior Verification Engineer for Advanced SoC Solutions

il y a 4 semaines

Paris, Île-de-France microTECH Global Limited Temps plein

Position:
Senior Verification Engineer

Company:
microTECH Global Limited

Contract:
Permanent

microTECH Global Limited is seeking a talented professional to join their innovative team in a stimulating and rewarding work environment.

The organization provides competitive remuneration and benefits, enabling employees to play a significant role in a rapidly expanding global team.

They are at the forefront of the System-on-Chip (SoC) revolution, collaborating with some of the most prominent and technically sophisticated clients worldwide.

Currently, they are focused on establishing a new team in the South of France and are looking for various profiles.

As a Senior Verification Engineer, you will collaborate with a skilled team to design and implement interconnect and memory hierarchy solutions for some of the most advanced mobile, telecom, automotive, and consumer SoC designs.

You will create designs using a powerful language that merges traditional RTL with cutting-edge software, delivering highly configurable, testable, and top-quality solutions.

You will be amazed at the diverse applications of your creations.

This role offers the chance to be part of a successful startup, influencing the development environment, architecture, verification processes, and everything in between – you will no longer feel isolated or merely a cog in the machine.

Your colleagues will be a seasoned team of industry professionals who are passionate about their work.

Key Responsibilities:

  • Development and debugging of advanced UVM-based test benches
  • Defining, documenting, developing, and executing RTL verification tests and coverage at the system level
  • Performance and power-aware verification
  • Managing regressions and debugging RTL designs in Verilog and SystemVerilog
  • Enhancing and refining verification processes, methodologies, and metrics
  • UVM expertise on complex SoC projects from test bench development to verification closure

Experience Requirements / Qualifications:

  • A minimum of 10 years of design and verification experience, with a preference for interconnect verification experience
  • Enhancements to verification flows using scripting languages such as Shell scripts, Python, and JavaScript
  • Strong debugging skills in RTL (Verilog) and UVM/C test benches
  • Experience integrating vendor-provided VIPs for unit and system-level verification
  • Familiarity with Arm AMBA protocols
  • This position involves high-performance, low-power designs on a highly visible project

Education Requirements:

  • Preferred: MS degree in Electrical Engineering, Computer Science, or equivalent; minimum requirement: BS degree

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