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PhD Position in Trustworthy AI Hardware Architectures

Il y a 2 mois


Rennes, Bretagne, France INRIA Temps plein
Job Description

Context and Background

As the demand for Artificial Intelligence (AI) applications continues to grow, there is an increasing need to distribute AI applications from the cloud to edge devices. This trend aims to address issues related to data privacy, bandwidth limitations, power consumption reduction, and low latency requirements, especially for real-time, mission- and safety-critical applications.

The direct consequence is the intense activity in designing custom and embedded AI Hardware architectures (AI-HW) to support energy-intensive data movement, speed of computation, and large memory resources that AI requires to achieve its full potential. Moreover, explaining AI decisions, referred to as eXplainable AI (XAI), is highly desirable in order to increase the trust and transparency in AI, safely use AI in the context of critical applications, and further expand AI application areas.

Research Focus

The goal of this PhD thesis is to study the impact of hardware faults not only on the AI decisions, but also on algorithms developed to explain AI (XAI) models. The objective is to make AI-HW reliable by understanding how hardware faults (due to variability, aging, external perturbations) can impact AI and XAI decisions and how to mitigate those impacts efficiently.

Key Responsibilities

  • Analyze the possible failure mechanisms affecting the hardware;
  • Derive the corresponding hardware faults (i.e., the logical representation of a failure mechanism);
  • Analyze their impact on AI and XAI results, in terms of accuracy degradation and determine their criticality;
  • Design low-cost fault tolerance approaches to efficiently detect/correct HW faults, thus ensuring the correctness of the hardware, with the goal to ensure a both correct AI and XAI decisions.

Requirements

  • Good knowledge of computer architectures and embedded systems;
  • Machine Learning (pytorch/tensorflow);
  • HW design: VHDL/Verilog basics, HW synthesis flow;
  • Basic programming knowledge (C/C++, python);
  • Experience with High Level Synthesis (HLS) is a plus;
  • Experience in fault tolerant architectures is a plus;

Language

Proficiency in written English and fluency in spoken English required.

Working Conditions

The candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner.

Benefits

  • Subsidized meals;
  • Partial reimbursement of public transport costs;
  • Possibility of teleworking (90 days per year) and flexible organization of working hours;
  • Partial payment of insurance costs;

Salary

Monthly gross salary amounting to 2100 euros for the first and second years and 2200 euros for the third year.