PhD Position in Trustworthy AI Hardware Architectures
il y a 4 semaines
Context and Background
As the demand for Artificial Intelligence (AI) applications grows, there is an increasing need to distribute AI applications from the cloud to edge devices. This trend aims to address issues related to data privacy, bandwidth limitations, power consumption reduction, and low latency requirements, especially for real-time, mission- and safety-critical applications.
The direct consequence is the intense activity in designing custom and embedded AI Hardware architectures (AI-HW) to support energy-intensive data movement, speed of computation, and large memory resources that AI requires to achieve its full potential. Moreover, explaining AI decisions, referred to as eXplainable AI (XAI), is highly desirable in order to increase the trust and transparency in AI, safely use AI in the context of critical applications, and further expand AI application areas.
AI-HW, similar to traditional computing hardware, is subject to faults that can have several sources: variability in fabrication process parameters, latent defects, or even environmental stress. One of the overlooked aspects is the role that HW faults can have in AI decisions. Indeed, there is a common belief that AI applications have an intrinsic high-level or resilience w.r.t. errors and noise. However, recent studies in the scientific literature have shown that AI-HW is not always immune to HW errors. This can jeopardize all the effort of having an explainable AI, leading any attempt to explainability to be either inconclusive or misleading.
Therefore, before explaining the decision of an AI algorithm - to gain confidence and trust in it - firstly the reliability of the hardware executing the AI algorithm needs to be guaranteed, even in the presence of hardware faults. In this way, trust and transparency of an implemented AI model can be ensured, not only in the context of mission- and safety-critical applications, but also in our everyday life.
Mission Confiee
The goal of the Ph.D. thesis is to study the impact of hardware faults not only on the AI decisions, but also on algorithms developed to explain AI (XAI) models. The objective is to make AI-HW reliable by understanding how hardware faults (due to variability, aging, external perturbations) can impact AI and XAI decisions and how to mitigate those impacts efficiently. The final goal is to enable the transparency of the AI-HW by designing self-explainable, trustworthy, reliable, and real-time verifiable AI hardware accelerators, capable of performing self-test, self-diagnosis, and self-correction.
Main Activities
- Analyze the possible failure mechanisms affecting the hardware;
- From the knowledge of failure mechanisms, derive the corresponding hardware faults (i.e., the logical representation of a failure mechanism);
- Analyze their impact on AI and XAI results, in terms of accuracy degradation and determine their criticality;
- Design low-cost fault tolerance approaches to efficiently detect/correct HW faults, thus ensuring the correctness of the hardware, with the goal to ensure a both correct AI and XAI decisions.
A possible approach to fault tolerance is to apply XAI techniques to produce explanations about the state of the hardware during inference and turn these explanations into actions to correct hardware faults. This Ph.D. subject targets the study of the impact of HW faults on both prototypes created by self-explainable models at training time and post-explanations at inference time. The starting point will be existing state-of-the-art AI HW accelerators optimized for energy efficiency and the outcome will be fault-tolerant versions, still energy efficient.
Required Technical Skills
- Good knowledge of computer architectures and embedded systems;
- Machine Learning (pytorch/tensorflow);
- HW design: VHDL/Verilog basics, HW synthesis flow;
- Basic programming knowledge (C/C++, python);
- Experience with High Level Synthesis (HLS) is a plus;
- Experience in fault tolerant architectures is a plus.
Candidates must have a Master's degree (or equivalent) in Computer Science, Computer Engineering, or Electrical Engineering.
Languages
Proficiency in written English and fluency in spoken English required.
Relational Skills
The candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner.
Other Valued Appreciated
Open-mindedness, strong integration skills, and team spirit.
Most Importantly, We Seek Highly Motivated Candidates
Advantages
- Subsidized meals;
- Partial reimbursement of public transport costs;
- Possibility of teleworking (90 days per year) and flexible organization of working hours;
- Partial payment of insurance costs.
Remuneration
Monthly gross salary amounting to 2100 euros for the first and second years and 2200 euros for the third year.
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