Hardware Design Concept Engineer

Read More **Job Overview**: Arm Physical Design Group (PDG) delivers the most comprehensive and sophisticated physical IP solution in the industry allowing the implementation of SoC designs. What Arm PDG offers is the oldest and most widely used on the market and includes logic IP, Standard Cell, Embedded Memory Compilers, Interface IP and Processor Optimization Pack (POPs). All of the Arm physical IP products are specifically optimized for each foundry and process technology node from 250nm to 3nm semiconductor processes for various founders. The Digital IPs, Reference Design and Validation (DRV) group engages in validation of the library products offered by Arm PDG on Silicon. We craft on test chips aimed to validate IP products (logic libraries, memories, IOs and Analog blocks) for ground breaking semiconductor processes (viz. >90nm, 90nm, 65nm, 40nm, 32nm, 28nm, 14nm, 7nm, 5nm and 3nm) for various leading foundries and IDMs around the world. We then characterize and test the silicon dies created by the foundries. These IPs are used by SOC companies & integrated in their design. It is imperative to validate them, to confirm their functionality to customers. To be a successful SoC Architect in the PDG Silicon Validation Team you will be persistent, outspoken, pragmatic, globally aware, ethically strong, believe in making profit and be prepared to work hard to get the job done time after time. Delivery of results is a meaningful measurement of success in this role. **Responsibilities**: - Define in collaboration with the SoC Architect Lead/Manager strategic decisions regarding Test Chip requirements and architecture concepts - Actively participate to the specification of new Test Chips and liaise with Silicon Validation Design Team for its implementation - Support Test chip bring up and silicon validation until final report - Collaborate with Engineering to enable smooth Test Chip integration of creative IPs **Required Skills and Expericence**: - Experience in Digital Design Concept architecture including Micro-architecture specification - Proven CPU memory system microarchitecture knowledge (high-performance caches, out-of-order execution and result return, cache coherence, virtual memory and address translation, system bus interfaces) - Excellent knowhow on CPU interconnect protocols CHI, AXI, AHB, APB and OCP - Excellent knowledge in multi clock domains and multi power domains systems handling and definition; system Power management definition - General understanding of semiconductor IP development threads and challenges - Experience in using simulation and formal verification tools **"Nice To Have" Skills and Experience**: - Knowledge in verification with System Verilog (UVM) skills - Knowledge of IP libraries components (Logic models, Timing, power and noise Models, Layout, Abstract) and their use in System on Chip development design flows (Simulation, DFT, Synthesis, Floor planning, Place and Route, STA Timing, IR Drop Analysis, Physical verification) - Perl and Python scripting appreciated - Ability to disseminate operational good practice through mentoring and influencing - Hardware security mitigation technics - Excellent learning skills. Highly motivated and have strong work ethic - Committed and highly driven to achieve objectives - Able to handle tasks through to completion - Self-sufficient - Able to define priorities and schedule own work as well as that of others - Excellent interpersonal skills and collaborative work style - Job requires extensive collaboration with Customers and internal organization (Engineering, Operations, Management) - Reliable and open-minded with a pragmatic approach to problem solving - Ability to work under pressure - Advanced interpersonal skills, oral and written - Ability to express ideas optimally and produce well constructed arguments - Willing to try new things to craft groundbreaking solutions for hard problems - Able to understand commercial realities and implications for projects and company **In Return**: We have a friendly and high-performance working environment, where Arm offers a competitive benefits package in France including: private medical insurance (employee and family), 25 days annual leave, supplementary pension and reduction in working hours (11 days). LI-MF1 **Equal Opportunities at Arm**: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic. **Hybrid Working at Arm**: Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. We empower groups/teams to determine their hybrid working pattern, with an expected minimum attendance in the office of 20% per month, depending on the work, level of experi