Phd Position F/m Fpga-based Near Memory Computing Architectures

Le descriptif de l’offre ci-dessous est en Anglais_

**Type de contrat**: CDD

**Niveau de diplôme exigé**: Bac + 5 ou équivalent

**Fonction**: Doctorant

**Contexte et atouts du poste**:
**Context and background**:
Moore's law has been driving computer performance for decades through CMOS down-scaling and architecture enhancements, resulting in doubled performance every 18 months. However, current technology encounters three significant challenges, including the leakage wall, reliability wall, and cost wall. Similarly, computer architectures are confronted with three walls: the memory wall, power wall, and instruction-level parallelism (ILP) wall. Numerous novel technologies and architectures are being researched to overcome these walls and enhance performance [1], [2].

Architects and designers are compelled to seek breakthroughs in computer architecture as the **total computation costs are dominated by the energy and performance costs of moving data** between the memory subsystem and the CPU. Indeed, modern computing systems experience a significant disparity between the performance and energy efficiency of computation and memory units. Such systems adopt a processor-centric method where data must travel to and from memory units through a relatively slow and power-intensive off-chip bus to computation units for processing. Consequently, workloads that heavily rely on data necessitate constant data movement between memory and CPU, leading to a **substantial overhead in execution time and energy efficiency** [3].

Modern field-programmable gate array (FPGA) with their on-chip URAMs and BRAMs, as well as access to high-bandwidth off-chip memory, can efficiently handle irregular memory access patterns and provide significantly higher memory bandwidth than CPUs. Their architectural flexibility makes them a popular choice for various data processing tasks, including machine learning and deep learning [4]-[6], database processing [7], [8], and networking [9].

**_ Near-memory computing _**_(_**_NMC_**_)_** is a **_memory-centric computing_** paradigm that has emerged as a promising solution to overcome the challenges mentioned above [1]. The goal of NMC is to **perform processing in proximity to the data** location - by placing compute units near the data - and it aims to minimize costly data transfers [2], [10].

Interestingly, **FPGA accelerators exhibit near-memory computation capabilities**, enabled by high-bandwidth memory (HBM), which are much closer to the logic than traditional DDR4-based FPGA boards. HBM technologies that use three-dimensional stacking enable processing close to memory by integrating logic and memory on a single chip. This innovative approach involves packing several layers vertically using through-silicon vias, which reduces memory access latency and energy consumption while increasing bandwidth [2].

[1] A. Gebregiorgis _et al._, “A Survey on Memory-Centric Computer Architectures,” _ACM J. Emerg. Technol. Comput. Syst._, p. 3544974, Jun. 2022, doi: 10.1145/3544974.
[2] V. Iskandar, M. A. A. E. Ghany, and D. Göhringer, “Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations,” _ACM Trans. Reconfigurable Technol. Syst._, vol. 16, no. 1, p. 16:1-16:32, Dec. 2022, doi: 10.1145/3547658.
[3] G. Singh _et al._, “FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications,” _IEEE Micro_, vol. 41, no. 4, pp. 39-48, Jul. 2021, doi: 10.1109/MM.2021.3088396.
[4] J. Fowers _et al._, “A Configurable Cloud-Scale DNN Processor for Real-Time AI,” in _2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)_, Jun. 2018, pp. 1-14. doi: 10.1109/ISCA.2018.00012.
[5] K. Kara, D. Alistarh, G. Alonso, O. Mutlu, and C. Zhang, “FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off,” in _2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)_, Apr. 2017, pp. 160-167. doi: 10.1109/FCCM.2017.39.
[6] Y. Umuroglu _et al._, “FINN: A Framework for Fast, Scalable Binarized Neural Network Inference,” in _Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays_, Monterey California USA, Feb. 2017, pp. 65-74. doi: 10.1145/3020078.3021744.
[7] Y. Choi, Y. Chi, W. Qiao, N. Samardzic, and J. Cong, “HBM Connect: High-Performance HLS Interconnect for FPGA HBM,” in _The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays_, New York, NY, USA, Feb. 2021, pp. 116-126. doi: 10.1145/3431920.3439301.
[8] K. Kara, J. Giceva, and G. Alonso, “FPGA-based Data Partitioning,” in _Proceedings of the 2017 ACM International Conference on Management of Data_, New York, NY, USA, May 2017, pp. 433-445. doi: 10.1145/3035918.3035946.
[9] M. Ruiz, D. Sidler, G. Sutter, G. Alonso, and S. López-Buedo, “Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack,” in _2019 29th International Conference on Field Programmable Logic and Appli