Phd Position F/m Reliable Deep Neural Network Hardware Accelerators

Le descriptif de l’offre ci-dessous est en Anglais
**Type de contrat**:
CDD
**Niveau de diplôme exigé**:
Bac + 5 ou équivalent
**Fonction**:
Doctorant
A propos du centre ou de la direction fonctionnelle
The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.
Contexte et atouts du poste
**Context & background**:
**References**:
[1] Y. LeCun, et al., “Deep learning,” Nature, vol. 521, no. 7553, pp. 436-444, May 2015, doi: 10.1038/nature14539.
**[2] B. Moons, et al, “14.5 Envision**: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy
- frequency
- scalable Convolutional Neural Network processor in 28nm FDSOI,” in IEEE ISSCC, 2017.
[3] C. Torres-Huitzil and B. Girau, “Fault and Error Tolerance in Neural Networks: A Review,” IEEE Access, 2017. [4] A. Lotfi et al., “Resiliency of automotive object detection networks on GPU architectures,” in IEEE ITC, 2019 [5] A. Ruospo, et al., “Investigating data representation for efficient and reliable Convolutional Neural Networks,” in Microprocessors and Microsystems, 2020
[6] F. K. Dosilovic, et al, “Explainable artificial intelligence: A survey,” in MIPRO, 2018.
**[7] N. Srivastava et al., “Dropout**: A simple way to prevent neural networks from overfitting,” Journal of Machine Learning Research, vol. 15, no. 1, pp. 1929-1958, 2014.
Mission confiée
**Ph.D. thesis goal**:
The reliability improvements obtained with the above-described methodology will be measured, and a design space exploration will be carried out to obtain different DNN HW accelerator implementations that will provide different trade-offs between fault tolerance and energy efficiency.
Principales activités
More in detail, the Ph.D. student will design and develop a methodology to perform large-scale fault analysis on state-of-the-art DNN hardware architectures. The fault analysis will determine the set of malignant HW faults that mostly impact classification accuracy (or other DNN objectives, such as image segmentation) during the inference phase.
In particular, the student will (i) design a novel framework that enables accurate fault sensitivity evaluation having the same accuracy of gate level while maintaining computational efficiency ; (ii) ensure that the framework effectively captures the intricate fault propagation characteristics of deep neural networks (DNNs) implemented in hardware.
Innovative methodologies will be explored to accelerate fault injection campaigns, such as hybrid analytical-empirical approaches and smart fault pruning techniques to minimize the number of required fault injections while maintaining high accuracy. Also, smart energy-efficient parallelization and distributed computing strategies to accelerate large-scale fault evaluation will be explored.
The proposed approach will be compared against state-of-the-art methodologies to validate improvements in speed and accuracy.
The developed framework will pave the way to innovative selective error correction mechanisms. A design space exploration will help to find the best solutions in terms of the trade-off between the fault tolerance level provided by protection mechanisms and the hardware overhead entailed in deploying these solutions.
Compétences
**Required technical skills**:
Good knowledge of computer architectures and embedded systems
**HW design**: VHDL/Verilog basics, HW synthesis flow
Programming knowledge (C/C++, python)
Basics of Machine Learning (pytorch/tensorflow)
Experience in fault-tolerant architectures is a plus
**Languages**: proficiency in written English and fluency in spoken English are required.
Other values appreciated are open-mindedness, strong integration skills, and team spirit.
Avantages
Subsidized meals
Partial reimbursement of public transport costs
Possibility of teleworking ( 90 days per year) and flexible organization of working hours
partial payment of insurance costs
Rémunération
monthly gross salary amounting to 2200 euros
Informations générales
**Thème/Domaine**:
Architecture, langages et compilation
**Ville**:
Rennes
**Centre Inria**:
Centre Inria de l'Université de Rennes
**Date de prise de fonction souhaitée**:
2025-06-01
**Durée de contrat**:
3 ans
**Date limite pour postuler**:
2025-04-30
Consignes pour postuler
**Please submit online**: your resume, cover letter and letters of recommendation eventually
**Sécurité défense**:
Ce poste est susceptible d’être affecté dans une zone à régime restrictif (ZRR), telle que définie dans le décret n°2011-1425 relatif à la protection du potentiel scientifique et technique de la nation (PPST). L’autorisation d’accès à une zone est délivrée par le chef d’établiss