Staff Hardware Verification Engineer
il y a 7 jours
**Vos principales responsabilités seront**:
Développement et débogage de bancs de test basés sur l'UVM avancé
Définir, documenter, développer et exécuter des tests de vérification RTL au niveau du système.
Vérification des performances et de la consommation d'énergie
Triage des régressions, débogage des conceptions RTL en Verilog et System Verilog
Contribuer à l'amélioration et au perfectionnement du processus de vérification, de la méthodologie et des mesures.
Expertise UVM sur des projets SoC complexes, du développement du banc d'essai à la clôture de la vérification.
**Expériences et**
**Qualifications**
**requises**:
- Doctorat ou Diplôme d’Ingénieur, Master en CS (Computer Science), ou équivalent de préférence
- Plus de 10 ans d'expérience dans la conception et la vérification numérique de SoC
- Amélioration des flux de vérification à l'aide de langages de programmation SW
- Solides compétences en débogage de RTL (Verilog) et de bancs de test UVM/C
- Expérience dans l'intégration des VIPs fournis par les fournisseurs pour la vérification des unités et des systèmes.
- Excellentes compétences en résolution de problèmes, en communication et en travail d'équipe,
- Autonome, capable de travailler avec un minimum de supervision.
- Bilingue en français et en anglais.
**Expériences additionnelles souhaitables**:
- Expérience des protocoles Arm AMBA
- Expérience avec les générateurs HW numériques, la méthodologie et le concept.
**Poste basé à Biot (06)** - télétravail possible 1 jour / semaine
**_English Version_**
**Key Responsibilities**:
- Advanced UVM based test bench development and debugging
- Defining, documenting, developing, and executing RTL verification test/coverage at system level
- Performance verification and power-aware verification
- Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
- Help improve and refine verification process, methodology, and metrics
- UVM expertise on complex SoC projects from test bench development to verification closure
**Experience Requirements / Qualifications**:
Required:
- 10+ years of experience in SoC digital design & verification
- Verification flow enhancements using SW programming languages
- Strong RTL (Verilog) and UVM/C test bench debugging skills
- Experience integrating vendor provided VIPs for unit and system level verification
- Excellent problem solving, strong communication and teamwork skills,
- Self-driven, able to work with minimum supervision.
- Bilingual in French and English
Desired:
- Experience with Arm AMBA protocols
- Experience with digital HW generators, methodology and concept.
**Education Requirements**:
- PhD or master’s degree in Computer Sciences or related field.
Poste based on Biot (06) - Remote possible 1 day / week
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