Layout Engineer
il y a 10 heures
**JOB SUMMARY**
As a Layout Engineer in our France, Alps based Memory IP Team, you will be contributing to all the layout and foundry related aspects of our state-of-the-art Memory Compiler Products. From the development of new compilers to the enhancement and maintenance of the existing ones, you will also be working on the back-end memory development and verification flows, as well as maintaining and updating the different back-end automation scripts that are also essential parts of the activity.
**ESSENTIAL JOB FUNCTIONS AND RESPONSIBILITIES; include but not limited to**:
- Layout implementation experience and following required specifications.
- A good understanding of memory compiler architectures and sub-blocks.
- Experience or good knowledge in FinFET is a plus.
- Experience driving circuit layout reviews with designers.
- A good understanding of LVS, DRC and ERC reports and be able to make the necessary corrections (Calibre).
- Worked in collaboration with designers to find the best design/layout compromises.
- Experience delivering quality work in a timely when under pressure.
- Knowledge of scripting is a plus (shell, skill, tcl).
- Knowledge of SLAM or Expert is a plus.
**QUALIFICATIONS AND REQUIRED EXPERIENCE**
- 5+ years of memory layout experience in the development of low power, high-performance, high-density SRAM/DPRAM/ROM memories.
- Excellent organizational, prioritization, time management skills and an unwavering commitment to integrity and professionalism.
- Self-starter and strong closer with multitasking ability.
- Language: French with good spoken and written English
- Working knowledge of Microsoft PowerPoint and Excel (including operations such as v-lookup, functions, pivot tables, etc.)
- Experience in semiconductor industry preferred.
- Experience in international and remote team building preferred.
**PHYSICAL REQUIREMENTS**
- Prolonged periods of sitting.
- Prolonged periods of typing
- Clarity of vision at approximately 20 inches or less (i.e., working with small objects or reading small print), including use of computers.
- Ability to lift (up) to 15 pounds at times.
**COMPANY INFORMATION**
For over three decades, Silvaco, based in Silicon Valley, California and with global locations around the world has solved semiconductor design challenges by offering affordable and competitive TCAD (Technology Computer Aided Design) software, EDA (Electronic Design Automation) software, proven design IP (intellectual property), and world class support to engineers and researchers across the globe. Silvaco solutions span from atoms to systems: starting with simulation of material behavior impacting semiconductor devices, to design and analysis of transistor circuits, and lastly providing IP blocks for systems-on-chip (SoC) designs. Our solutions are deployed in production flows across broad industry segments such as leading display companies, automotive OEM suppliers, and top Memory, 5G, and IoT (internet of things) providers.
**WE ARE AN EQUAL OPPORTUNITY EMPLOYER**
At Silvaco, we do not discriminate based upon race, religion, color, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
If you need assistance or an accommodation due to a disability, please contact us at
408.567.1000
.
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