Chip-package Codesign Engineering

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**Are you enthusiastic about new technologies? This position is an excellent opportunity for an expert and highly motivated chip design engineer to join the hardworking Advanced Product team and shape the future.

This diverse, engineering-centric group invents, defines, and develops innovative implementations of optimized physical IP designs in silicon. With an emphasis on chip-level integration, you will partner with various design teams with a focus on chip-package optimization.

We pursue next-generation Arm CPUs, GPUs, advanced memory IP, and are inventing new concepts that will power billions of devices worldwide. As chip-package codesign engineer you will be focused on chip performance both before and after packaging, and having an impact on overall SIP (system in package) performance, which is crucial when implementing designs in the latest process nodes.

**Responsibilities**:
You will design aspects of various test chip prototypes, working alongside package design engineers to create the best system-in-package (SIP) with your focus being chip back-end design. This requires a SIP solution to assure quality and optimal performance. From early chip floor-planning through silicon tape-out, you will optimize block placement, IO planning, and RDL routing alongside package designers creating the final package for the SIP. You'll need to use codesign planning tools, and perform chip model extractions to provide to package designers. Your role is instrumental to the success of Arm using your skills and knowledge to assure excellent performance of the SIP.

Broadly speaking, you will work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP, with a package-aware focus. This includes a close working relationship to the package design team members, who will be co-optimizing the package to the chip.

To be a successful contributor inside your team you are persistent, pragmatic, globally aware, ethically strong, believe in making profit and be prepared to work hard to get the job done time after time. Delivery of results is an important measurement of success in this role. You will contribute to an exciting engineering-focused environment in a field that is at the forefront of new technology in the industry

**Required Skills and Experience**:

- Experience performing die floor-planning, including hard macro block placement, RDL routing optimization, IO pad ring creation and bump pattern with assignments
- You have an understanding of package constraints imposed on chip design, and are able to co-optimize the chip-planning with the package engineering team
- You have experience in thermal and power activity model extraction, and the data structures required for package engineering to perform chip-aware package analysis.
- Experience of working with remote and international teams
- Ability to document and train others on work developed

***“Nice To Have” Skills and Experience**:

- Knowledge of advanced packaging technologies, assembly processes, and their corresponding requirements and constraints
- Familiarity working with stacked dies, 3D/2.5D package structures with chip-level constraints and requirements, such as TSV integration
- Experience with package level analysis and design tools

***It is important for you to be**:

- Committed and highly driven to achieve objectives
- Able to express ideas and communicate effectively
- Reliable and open-minded with a pragmatic approach to problem solving
- Able to work under pressure
- Excellent with interpersonal skills, oral and written
- Able to understand commercial realities and implications for projects and the company

***In Return**:
We have a friendly and high-performance working environment, where Arm offers a competitive benefits package in France including: private medical insurance (employee and family), 25 days annual leave, 20-day sabbatical every four years, supplementary pension and reduction in working hours (11 days).

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Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic.