Exploring The Generalizability of Ml-driven Model Generation for Hw Design

Description du poste

**Domaine**:

- Composants et équipements électroniques

**Contrat**:

- Stage

**Intitulé de l'offre**:

- Exploring the Generalizability of ML-driven Model Generation for HW Design H/F

**Sujet de stage**:
The Environmental Design and Architecture Laboratory (LECA), within the Digital Systems and Integrated Circuits Department (DSCIN), is a multidisciplinary technological research team comprising experts in hardware IP design and simulation tools. A key contribution of the Lab lies in its innovative methodologies and tools for automating model generation through machine learning techniques. In particular, the kMLeon tool facilitates the automatic generation of extra-functional models, such as performance and power ones.

This internship provides a valuable opportunity to gain hands-on experience with machine learning techniques for model generation and HW/SW co-design, contributing to innovative approaches in EDA (Electronic Design Automation).

**Durée du contrat (en mois)**:

- 5 à 7 mois

**Description de l'offre**:

- This internship aims to develop a methodology for constructing machine learning (ML)-based models that effectively generalize across the design space of the CVA6 processor. The objective is to predict performance, power, and area (PPA) metrics based on hardware configurations while reducing the number of required simulations. One aspect of the internship involves conducting a comprehensive state-of-the-art (SoA) review of advanced ML techniques, including Generative Adversarial Networks (GANs) for data augmentation, active learning for efficient simulation selection, and regression models for predictive analysis.
- The intern will:

- Conduct a state-of-the-art review to evaluate existing ML techniques for configuration-aware modeling.
- Define and simulate, using an internal framework, a representative subset of CVA6 configurations to generate PPA metrics.
- Explore and prototype ML approaches, such as GANs, active learning, and regression models.
- Train and validate the models to ensure effective generalization across unseen configurations.
- Propose a scalable and reproducible methodology for hardware configuration-aware modeling.
- If time allows, the intern may also explore using the developed model for architectural exploration to efficiently identify optimized configurations.
- Required Level: Master's degree or Engineering diploma
Duration: 6 months
Skills Required: Familiarity with AI, knowledge of Computer Architecture, proficiency in Python and C/C++, and experience with Git
Other Qualities: Strong command of English, collaborative mindset, and a genuine curiosity
Application Materials: Please submit a CV together with academic transcripts and a cover letter
- In line with CEA's commitment to integrating people with disabilities, this job is open to all._

Localisation du poste

**Site**:

- Saclay

**Localisation du poste**:

- France, Ile-de-France

**Ville**:

- Palaiseau

Demandeur

**Disponibilité du poste**:

- 15/03/2025

Informations générales

**Entité de rattachement**:
Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.

Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.

Implanté au cœur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.

Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales:

- La conscience des responsabilités
- La coopération
- La curiosité

**Référence**:2025-35215