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Senior FPGA
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About Us
Gramian Consultancy is a boutique consultancy specializing in IT professional services and engineering talent solutions. With a strong background in engineering and leadership, we help companies build high-performing teams by matching them with professionals who truly fit their needs.
About the Role
Our client is a well-established European engineering organization working on complex SoC-based platforms with strict real-time, throughput, latency, and synchronization constraints. As part of continued growth driven by client demand, they are creating a new position for a Senior FPGA / ASIC Design Engineer to contribute to advanced microelectronics projects.
In this role, you will take ownership of complex FPGA developments, working closely with hardware and embedded software teams on high-performance architectures used in regulated and technically demanding environments.
This is a hands-on technical position with strong architectural responsibility and exposure to end-to-end FPGA development cycles.
Location: HYBRID
Office Location: Paris (Southern suberb)
Contract: Permanent
Language: English
Interview Process: Intro Call + 3 Client Interviews
Responsibilities
- Define FPGA / IP architectures and detailed technical specifications
- Design and adapt verification environments, including complex testbenches (UVM when applicable)
- Implement real-time processing blocks under strong performance constraints (latency, throughput, synchronization)
- Integrate high-speed protocols such as Ethernet, PCIe, DisplayPort, HDMI, and related PHY chains
- Perform IP integration, RTL simulation, logic synthesis, place & route, and on-target validation
- Collaborate closely with hardware and embedded software teams to ensure functional and timing consistency
- Contribute to design and code reviews and provide technical guidance to junior engineers
- Participate in projects involving SoC architectures and advanced signal processing pipelines
- Master's degree (or equivalent) in Electronics or Microelectronics Engineering
- Minimum 5 years of hands-on experience in FPGA / ASIC design (mandatory)
- 5–10 years of professional experience in complex environments such as Telecom, Aerospace, Rail, Space, or Energy
- Strong command of VHDL, Verilog, SystemVerilog, and SystemC / C++
- Proven experience building complex testbenches (UVM strongly preferred)
- Solid understanding of video and high-speed interfaces: HDMI, DisplayPort, Ethernet, PCIe, 4G/5G modem chains, PHY architectures
- Experience with industry tools such as Cadence Xcelium, Siemens ModelSim, Vivado, Quartus, Synplify
- Good understanding of signal processing algorithms and hardware implementation
- Comfortable working across HW/SW boundaries in multidisciplinary teams
- Professional technical English
- Must be eligible for defense security clearance
