Senior Physical Design Engineer

il y a 4 jours

Paris, Île-de-France BREAM & LAANAIA Temps plein

Notre client est un acteur de référence mondial pour le développement de SoC utilisés dans les secteurs automotive, IA, mobile, edge computing, data centers et spatial. Il développe des IP hautement configurables intégrées dans des systèmes complexes soumis à de fortes exigences de performance, scalabilité et fiabilité.

Contexte du poste

Dans un environnement SoC avancé, multi-nœuds et multi-technologies, vous interviendrez sur tout le flow d'implémentation physique d'IP complexes et paramétrables.

Le rôle combine expertise hands-on, conception méthodologique, debug avancé et interaction transverse avec les équipes hardware et software.

Responsabilités clés

  • Concevoir, développer et maintenir des flows d'implémentation physique robustes et industrialisés (Place & Route, CTS, STA, signoff) sur outils Cadence (Innovus/Tempus) et Synopsys (ICC2/PrimeTime)
  • Définir et optimiser les contraintes de timing, power et area pour des IP fortement configurables
  • Mettre en place des stratégies de vérification physique et de couverture système (QoR, PPA, convergence timing)
  • Analyser, qualifier et améliorer la qualité des résultats sur différentes configurations et technologies
  • Mener des activités de debug avancé : violations timing, congestion, routage, CTS, SI, etc.
  • Concevoir et exécuter des plans de test automatisés pour la validation des flows
  • Contribuer à l'évolution des méthodologies PD, en intégrant les évolutions des outils EDA et les meilleures pratiques du marché comme référent technique
  • Collaborer étroitement avec les équipes RTL, architecture, software et validation pour assurer la cohérence HW/SW
  • Interagir avec les équipes internes et les utilisateurs finaux pour comprendre les exigences et proposer des évolutions techniques

Profil recherché

  • Diplôme Master, Bac+5 ou Doctorat en électronique, microélectronique ou informatique avec 8 ans et plus d'expérience en conception et implémentation physique de circuits digitaux complexes
  • Expertise confirmée en Physical Design flows (Cadence & Synopsys)
  • Très forte capacité en debug d'implémentation physique et analyse timing
  • Solides connaissances en programmation matérielle (system Verilog) et logicielle (type python/TCL)
  • Capacité à travailler en totale autonomie
  • Excellentes compétences de communication, écrite et orale
  • Français et anglais courants

Pourquoi ce poste est attractif

  • Position Senior / Expert, avec une forte influence sur les choix techniques
  • Environnement EDA & SoC de pointe, au contact direct des évolutions industrielles
  • Problématiques complexes et non routinières (configurabilité, vérification, industrialisation)
  • Forte exposition transverse et directe avec des équipes internationales : architecture, hardware, software

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