PhD Position in AI-Assisted Generation of High-Level Models and Simulators for Hardware Design
Il y a 6 mois
Position description
Category
Electronics components and equipments
Contract
Fixed-term contract
Job title
PhD Position in AI-Assisted Generation of High-Level Models and Simulators for Hardware Design
Socio-professional category
Non Cadre
Contract duration (months)
36
Job description
Simulation tools are essential for the design and validation of digital circuits. They use different levels of abstraction to facilitate hardware/software co-design and co-validation. Architecture simulators, called Instruction Set Simulators (ISSs), provide high-level abstraction for fast functional verification and early design space exploration, while Register Transfer Level (RTL) simulators provide detailed circuit-level implementation for accurate analysis but with longer simulation times.
Faced with accelerated development schedules together with tool and resource constraints, hardware designers often start with RTL development and defer the construction of an ISS. However, as the design process progresses, the need to create ISSs becomes apparent, particularly for tasks such as software validation and design space exploration of next-generation hardware.
Creating ISSs manually presents significant challenges, as it is both time-consuming and error-prone. Further complexity is introduced by the need to ensure equivalence between ISS and RTL. There is therefore an urgent need for innovative methods to automate the generation of an ISS when the RTL is available.
The generation process of an ISS consists mainly of extracting architectural states and deriving instruction execution functions [1, 2]. An ISS is then constructed by seamlessly integrating the architectural states and the instruction execution functions, ensuring an accurate representation of the hardware's functional behaviour.
The goal of the thesis is to design a methodology implemented in a tool that takes low-level RTL models as input and automatically generates an ISS by exploiting recent advances in machine learning (ML) such as Graph Neural Networks [3], and compilation flows such as MLIR [4], in the field of electronic design automation (EDA). The expected result is a complete flow for the automatic generation of ISS from RTL, ensuring by construction the semantic consistency between the two levels.
The results of this thesis will be the subject of presentations at international conferences and in scientific journals.
References
[1] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Generating architecture-level abstractions from RTL designs for processors and accelerators part I: Determining architectural state variables." ICCAD, 2021.
[2] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Automatic generation of architecture-level models from RTL designs for processors and accelerators." DATE, 2022.
[3] Chowdhury, Subhajit Dutta, Kaixin Yang, and Pierluigi Nuzzo. "ReIGNN: State register identification using graph neural networks for circuit reverse engineering." ICCAD, 2021.
[4] Lattner, Chris, et al. "MLIR: Scaling compiler infrastructure for domain specific computation." CGO, 2021.
Applicant Profile
Master's degree in Computer Science/Electronics. Good experience/knowledge in Machine Learning. Experience/knowledge in digital electronics design. Excellent programming skills in Python and C++. Proficiency in VHDL and/or Verilog programming will be a plus. Good analytical and experimental skills will be highly valued.
Position location
Site
Saclay
Job location
France, Ile-de-France
Location
Palaiseau
Requester
Position start date
01/10/2024
-
Palaiseau, Île-de-France CEA Temps pleinJob SummaryWe are seeking a highly motivated PhD researcher to join our team at CEA, working on the development of AI-assisted generation of high-level models and simulators for hardware design.Key ResponsibilitiesDesign and implement a methodology for automatic generation of Instruction Set Simulators (ISSs) from Register Transfer Level (RTL) models using...
-
Senior Research Engineer: AI-Assisted Hardware Design and Simulation
il y a 3 semaines
Palaiseau, Île-de-France CEA Temps pleinJob Title: PhD Position in AI-Assisted Generation of High-Level Models and SimulatorsCategory: Electronics components and equipmentsContract: Fixed-term contractSocio-professional category: Non CadreContract duration (months): 36Job description:The design and validation of digital circuits rely heavily on simulation tools. These tools employ different levels...
-
Palaiseau, France CEA Temps pleinPosition description Category Electronics components and equipments Contract Fixed-term contract Job title Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC Designs H/F Socio-professional category Executive Contract duration (months) 24 Job description We are looking for a...
-
Improving The Effectiveness of Llm-assisted Iss
il y a 1 mois
Palaiseau, France CEA Temps pleinPosition description **Category**: - Mathematics, information, scientific, software **Contract**: - Internship **Job title**: - Improving the Effectiveness of LLM-Assisted ISS Generation from Design Specification H/F **Subject**: - The internship aims to enhance the performance of large language models (LLMs) in generating Instruction Set Simulator...
-
Palaiseau, France CEA Temps pleinPosition description Category Mathematics, information, scientific, software Contract Internship Job title Improving the Effectiveness of LLM-Assisted ISS Generation from Design Specification H/F Subject The internship aims to improve LLM performance in generating ISS code by using RL to optimize prompt tuning and automate...
-
Phd Position F/m Design and Implementation of a
Il y a 2 mois
Palaiseau, France Inria Temps pleinLe descriptif de l’offre ci-dessous est en Anglais_ **Type de contrat **:CDD **Niveau de diplôme exigé **:Bac + 5 ou équivalent **Fonction **:Doctorant **A propos du centre ou de la direction fonctionnelle**: The Inria Saclay-Île-de-France Research Centre was established in 2008. It has developed as part of the Saclay site in partnership with...
-
Palaiseau, France CEA Temps pleinDescription de l'offre The Environmental Design and Architecture Laboratory (LECA), within the Digital Systems and Integrated Circuits Department (DSCIN), is a multidisciplinary technological research team comprising experts in hardware IP design and simulation tools. A key contribution of the Lab lies in its innovative methodologies and tools for...
-
Palaiseau, France Inria Temps pleinA propos du centre ou de la direction fonctionnelleThe Inria Saclay-Île-de-France Research Centre was established in 2008. It has developed as part of the Saclay site in partnership with Paris-Saclay University and with the Institut Polytechnique de Paris . The centre has 40 project teams , 32 of which operate jointly with Paris-Saclay University and the...
-
PhD Researcher in AI Model Audit and Uncertainty Quantification
il y a 2 semaines
Palaiseau, Île-de-France INRIA Temps pleinAbout the JobThis PhD research position is part of a team at Inria Saclay, focused on developing mathematical tools for auditing complex AI systems. The goal is to provide actionable insights into the reliability of these systems, especially in high-stakes applications like healthcare.Company OverviewInria is a French national research institute with a...
-
Palaiseau, France INRIA Temps pleinPhD Position F/M Efficient Space and Garbage Collection for Functional Languages and Lambda Calculi Le descriptif de l’offre ci-dessous est en Anglais Type de contrat : CDD Niveau de diplôme exigé : Bac + 5 ou équivalent Fonction : Doctorant A propos du centre ou de la direction fonctionnelle The Inria...
-
Assistant Professor in Generative Models for
il y a 1 mois
Palaiseau, France Institut Mines-Télécom Temps plein**Who are we?** Télécom Paris, a school of the IMT (Institut Mines-Télécom) and a founding member of the Institut Polytechnique de Paris, is one of the top 5 French general engineering schools. The guiding mission of Télécom Paris is to train, imagine and undertake to design digital models, technologies and solutions for a society and economy that...
-
Palaiseau, Île-de-France INRIA Temps pleinBackground and MotivationThe increasing reliance on complex AI systems in various sectors has led to a growing demand for auditing these systems to ensure their safety and effectiveness. However, the probabilistic nature of modern AI presents a challenge in achieving certitude in individual cases. From an engineering standpoint, uncertainty quantification is...
-
Palaiseau, Île-de-France INRIA Temps pleinContext and SkillsThe postdoctoral position is open in the framework of the AI4scMED consortium. The successful candidate is expected to have a strong background in mathematical and/or computational biology, with a focus on multiscale modeling.Research ProjectThe postdoc fellow will work on developing a multiscale model of single cell-based dynamics of...
-
Palaiseau, France INRIA Temps pleinPhD Position F/M PhD position in Quantum Information Theory Le descriptif de l’offre ci-dessous est en Anglais Type de contrat : CDD Niveau de diplôme exigé : Bac + 5 ou équivalent Fonction : Doctorant A propos du centre ou de la direction fonctionnelle The Inria Saclay-Île-de-France Research Centre was established in...
-
Cutting-Edge Research Engineer in AI-Driven SoC Design and Simulation
il y a 3 semaines
Palaiseau, Île-de-France CEA Temps pleinAbout the JobWe are seeking a highly skilled Research Engineer to join our team at CEA, a leading institution in Electronic Design Automation (EDA) and Artificial Intelligence (AI). The successful candidate will be responsible for developing cutting-edge technology in the field of AI-driven SoC design and simulation.Key ResponsibilitiesDevelop and implement...
-
Palaiseau, France Institut Mines-Télécom Temps pleinWho we are ?Télécom Paris, part of the IMT (Institut Mines-Télécom) and a founding member of the Institut Polytechnique de Paris, is one of France's top 5 general engineering schools.The mainspring of Télécom Paris is to train, imagine and undertake to design digital models, technologies and solutions for a society and economy that respect people and...
-
Palaiseau, France CEA Temps pleinPosition description Category Information system Contract Postdoc Job title Postdoctoral position in AI and SW engineering at CEA LIST near Paris H/F Subject The goal of this post-doc is to explore generative AI in the context of system modeling and associated tool support. For instance, AI assistance can support the...
-
PhD Position in Unbounded Hyperbolic Media Research
il y a 4 semaines
Palaiseau, Île-de-France INRIA Temps pleinJob Context and RequirementsINRIA is seeking a highly skilled candidate to fill a PhD position in the field of hyperbolic metamaterials. The successful applicant will be responsible for developing numerical analysis techniques for wave propagation in these unique materials.The ideal candidate will have a strong background in numerical analysis, solid complex...
-
Palaiseau, France CEA Temps pleinPosition description Category Electronics components and equipments Contract Fixed-term contract Job title Post-doc application of formal methods for interferences management H/F Socio-professional category Executive Contract duration (months) 18 Job description Within a multidisciplinary technological research...
-
Benchmarking The Scalability of Model-checker-based
Il y a 2 mois
Palaiseau, France CEA Temps pleinDescription du poste **Domaine**: - Mathématiques, information scientifique, logiciel **Contrat**: - Stage **Intitulé de l'offre**: - Benchmarking the scalability of model-checker-based detection of timing anomalies H/F **Sujet de stage**: - Safety-critical systems such as autonomous vehicles and modern avionic computers have to satisfy strong...
